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检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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An FPGA-based RNN-T inference accelerator with PIM-HBM 22

An FPGA-based RNN-T inference accelerator with PIM-HBM

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Kang, Shin-Haeng Lee, Sukhan Kim, Byeongho Kim, Hweesoo Sohn, Kyomin Kim, Nam Sung Lee, Eojin Samsung Electronics Hwaseong Korea Republic of Seoul National University Seoul Korea Republic of Inha University Incheon Korea Republic of

ISBN: (纸本)9781450391498

In this paper, we implemented a world-first RNN-T inference accelerator using FPGA with PIM-HBM that can multiply the internal bandwidth of the memory. The accelerator offloads matrix-vector multiplication (GEMV) operations of LSTM layers in RNN-T into PIM-HBM, and PIM-HBM reduces the execution time of GEMV significantly by exploiting HBM internal bandwidth. To ensure that the memory commands are issued in a pre-defined order, which is one of the most important constraints in exploiting PIM-HBM, we implement a direct memory access (DMA) module and change configuration of the on-chip memory controller by utilizing the flexibility and reconfigurability of the FPGA. In addition, we design the other hardware modules for acceleration such as non-linear functions (i.e., sigmoid and hyperbolic tangent), element-wise operation, and ReLU module, to operate these compute-bound RNN-T operations on FPGA. For this, we prepare FP16 quantized weight and MLPerf input datasets, and modify the PCIe device driver and C++ based control codes. On our evaluation, our accelerator with PIM-HBM reduces the execution time of RNN-T by 2.5 × on average with 11.09% reduced LUT size and improves energy efficiency up to 2.6 × compared to the baseline. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models 24

Accounting for Floorplan Irregularity and Configuration Depe...

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24th international symposium on Quality Electronic Design (ISQED)

作者： Barajas, Gabriel Greene, Jonathan W. Li, Fei Tandon, James Microchip San Jose CA 95134 USA Cambios Comp LLC Palo Alto CA USA Calif State Univ East Bay Hayward CA USA

ISBN: (纸本)9798350334753

Accurate delay estimates for a user application implemented in a field-programmable gate Array (FPGA) are essential for a quality FPGA timing flow and to avoid leaving performance on the table. FPGA inter-cluster routing consists of wire segments of a limited number of types which repeat in a somewhat regular pattern, interconnected by configurable muxes. The delay at any fanout of a segment can be significantly impacted by configuration-dependent capacitive loading related to other fanouts. Also, the insertion of RAM and math blocks into the FPGA floorplan introduces irregular stretching of the wire segments, altering their delays. We explain why and how commercial FPGA software typically employs a parameterized model for the delay at each fanout of a segment, based on the configuration and the irregularities present, with the parameters determined by fitting SPICE simulation data for a representative sample of cases. We propose incorporating readily-computed common path resistance values into the model. This enables high accuracy with fewer parameters and without the large amounts of SPICE data that would otherwise be required to explore interactions between floorplan irregularities and the set of active fanouts. In combination with other features of our models, errors in segment delay are reduced by almost half.

关键词： field-programmable gate arrays FPGAs delay estimation Elmore delay common path resistance

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High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMV 22

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs...

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Du, Yixiao Hu, Yuwei Zhou, Zhongchun Zhang, Zhiru Cornell University IthacaMI United States Tsinghua University Beijing China

ISBN: (纸本)9781450391498

Sparse linear algebra operators are memory bound due to low compute to memory access ratio and irregular data access patterns. The exceptional bandwidth improvement provided by the emerging high-bandwidth memory (HBM) technologies, coupled with the ability of FPGAs to customize the memory hierarchy and compute engines, brings the potential to significantly boost the performance of sparse linear algebra operators. In this paper we identify four challenges when developing high-performance sparse linear algebra accelerators on HBM-equipped FPGAs - - low HBM bandwidth utilization with conventional sparse storage, limited on-chip memory capacity being the bottleneck when scaling to multiple HBM channels, low compute occupancy due to bank conflicts and inter-iteration carried dependencies, and timing closure on multi-die heterogeneous fabrics. We conduct an in-depth case study on sparse matrix-vector multiplication (SpMV) to explore techniques that tackle the four challenges. These techniques include (1) a customized sparse matrix format tailored for HBMs, (2) a scalable on-chip buffer design that combines replication and banking, (3) best practices of using HLS to implement hardware modules that dynamically resolve bank conflicts and carried dependencies for achieving high compute occupancy, and (4) a split-kernel design methodology for frequency optimization. Using the techniques, we demonstrate HiSparse, a high-performance SpMV accelerator on a multi-die HBM-equipped FPGA device. We evaluated HiSparse on a variety of matrix datasets. The results show that HiSparse achieves a high frequency and delivers promising speedup with increased bandwidth efficiency when compared to prior arts on CPUs, GPUs, and FPGAs. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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RapidStream: Parallel Physical Implementation of FPGA HLS Designs 22

RapidStream: Parallel Physical Implementation of FPGA HLS De...

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Guo, Licheng Maidee, Pongstorn Zhou, Yun Lavin, Chris Wang, Jie Chi, Yuze Qiao, Weikang Kaviani, Alireza Zhang, Zhiru Cong, Jason University of California Los Angeles Los AngelesCA United States Xilinx Inc. San JoseCA United States Ghent University Ghent Belgium Cornell University IthacaMI United States

ISBN: (纸本)9781450391498

FPGAs require a much longer compilation cycle than conventional computing platforms like CPUs. In this paper, we shorten the overall compilation time by co-optimizing the HLS compilation (C-to-RTL) and the back-end physical implementation (RTL-to-bitstream). We propose a split compilation approach based on the pipelining flexibility at the HLS level, which allows us to partition designs for parallel placement and routing then stitch the separate partitions together. We outline a number of technical challenges and address them by breaking the conventional boundaries between different stages of the traditional FPGA tool flow and reorganizing them to achieve a fast end-to-end compilation. Our research produces RapidStream, a parallelized and physical-integrated compilation framework that takes in an HLS dataflow program in C/C++ and generates a fully placed and routed implementation. When tested on the Xilinx U250 FPGA with a set of realistic HLS designs, RapidStream achieves a 5-7X reduction in compile time and up to 1.3X increase in frequency when compared to a commercial-off-the-shelf toolchain. In addition, we provide preliminary results using a customized open-source router to reduce the compile time up to an order of magnitude in the cases with lower performance requirements. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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Extending Memory Compatibility with Yosys Front-End in the VTR Flow 34

Extending Memory Compatibility with Yosys Front-End in the V...

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34th international Workshop on Rapid System Prototyping - Shortening the Path from Specification to Prototype

作者： Azadi, Alireza Arjomand, Amir Kent, Kenneth B. Univ New Brunswick Fredericton NB Canada

ISBN: (纸本)9798400704109

Verilog-to-routing (VTR) is an open source Computer Aided Design (CAD) framework that is widely used for research purposes. VTR provides researchers with a comprehensive set of benchmarks and FPGA architectures to test, compare and verify their designs and CAD algorithms. VTR employs Odin, Yosys and a combination of Yosys+Odin as its front-ends for elaborating digital designs written in Verilog. Yosys is a standalone synthesis framework that is maintained separately. In order to take advantage of Yosys' latest upgrades, it is essential to upgrade VTR in tandem with Yosys to keep up with its latest changes. In our study, we investigated the integration of the latest available version of Yosys into VTR. In the course of this research, we encountered a challenge stemming from a memory incompatibility in newer versions of Yosys. Our primary research question became how to effectively facilitate netlist conversion from Yosys to Odin to overcome this incompatibility issue. We then showcase how this upgrade affects our benchmark suite, highlighting the notable changes in circuit quality and the tool performance. Our post-upgrade evaluations reveal that the STA (static timing analysis) time of placement and the placement time itself exhibited improvements of up to 11.53% and 10.43%, respectively.

关键词： field programmable gate arrays Electronic Design Automation Free and Open Source Software Yosys Verilog to Routing

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REMOT: A Hardware-Software Architecture for Attention-Guided Multi-Object Tracking with Dynamic Vision Sensors on FPGAs 22

REMOT: A Hardware-Software Architecture for Attention-Guided...

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Gao, Yizhao Wang, Song So, Hayden Kwok-Hay University of Hong Kong Hong Kong

ISBN: (纸本)9781450391498

In contrast to conventional vision sensors that produce images of the entire field-of-view at a fixed frame rate, dynamic vision sensors (DVS) are neuromorphic devices that only produce sparse events in response to changes in light intensity local to each pixel, making them promising technologies for use in demanding edge scenarios where energy-efficient intelligent computations are needed. While several early research have demonstrated promising results in performing high-level machine vision tasks using vision events only, these algorithms are often too complex for real-time deployments in edge systems with limited processing and storage capabilities. In this work, a novel hardware-software architecture, called REMOT, is proposed to leverage the unique properties of DVS to perform real-time multi-object tracking (MOT) on FPGAs. REMOT incorporates a parallel set of reconfigurable hardware attention units (AUs) that work in tandem with a modular attention-guided software framework running in the attached processor. Each hardware AU autonomously adjusts its region of attention by processing each vision event as they are produced by the DVS. Using information aggregated by the AUs, high-level analyses are performed in software. To demonstrate the flexibility and modularity of REMOT, a family of MOT algorithms with different hardware-software configurations and tradeoffs have been implemented on 2 different edge reconfigurable systems. Experimental results show that REMOT is capable of processing 0.43-2.22 million events per second at 1.75-5.68 watts, making them suitable for real-time operations while maintaining good MOT accuracy in our target datasets. When compared with a software-only implementation using the same edge platforms, our HW-SW implementation results in up to 33.6 times higher event processing throughput and 25.9 times higher power efficiency. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference 22

Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient...

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Wang, Erwei Davis, James J. Stavrou, Georgios-Ilias Cheung, Peter Y. K. Constantinides, George A. Abdelfattah, Mohamed Imperial College London London United Kingdom Cornell University New YorkNY United States

ISBN: (纸本)9781450391498

FPGA-specific DNN architectures using the native LUTs as independently trainable inference operators have been shown to achieve favorable area-accuracy and energy-accuracy tradeoffs. The first work in this area, LUTNet, exhibited state-of-the-art performance for standard DNN benchmarks. In this paper, we propose the learned optimization of such LUT-based topologies, resulting in higher-efficiency designs than via the direct use of off-the-shelf, hand-designed networks. Existing implementations of this class of architecture require the manual specification of the number of inputs per LUT, K. Choosing appropriate K a priori is challenging, and doing so at even high granularity, e.g. per layer, is a time-consuming and error-prone process that leaves FPGAs' spatial flexibility underexploited. Furthermore, prior works see LUT inputs connected randomly, which does not guarantee a good choice of network topology. To address these issues, we propose logic shrinkage, a fine-grained netlist pruning methodology enabling K to be automatically learned for every LUT in a neural network targeted for FPGA inference. By removing LUT inputs determined to be of low importance, our method increases the efficiency of the resultant accelerators. Our GPU-friendly solution to LUT input removal is capable of processing large topologies during their training with negligible slowdown. With logic shrinkage, we better the area and energy efficiency of the best-performing LUTNet implementation of the CNV network classifying CIFAR-10 by 1.54× and 1.31×, respectively, while matching its accuracy. This implementation also reaches 2.71× the area efficiency of an equally accurate, heavily pruned BNN. On ImageNet with the Bi-Real Net architecture, employment of logic shrinkage results in a post-synthesis area reduction of 2.67× vs LUTNet, allowing for implementation that was previously impossible on today's largest FPGAs. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores 22

N3H-Core: Neuron-designed Neural Network Accelerator via FPG...

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Gong, Yu Xu, Zhihan He, Zhezhi Zhang, Weifeng Tu, Xiaobing Liang, Xiaoyao Jiang, Li Shanghai Qi Zhi Institute Shanghai China Shanghai Jiao Tong University Shanghai China Alibaba Group US Inc. San Diego United States Alibaba Group Hangzhou China

ISBN: (纸本)9781450391498

Accelerating the neural network inference by FPGA has emerged as a popular option, since the reconfigurability and high performance computing capability of FPGA intrinsically satisfies the computation demand of the fast-evolving neural algorithms. However, the popular neural accelerators on FPGA (e.g., Xilinx DPU) mainly utilize the DSP resources for constructing their processing units, while the rich LUT resources are not well exploited. Via the software-hardware co-design approach, in this work, we develop an FPGA-based heterogeneous computing system for neural network acceleration. From the hardware perspective, the proposed accelerator consists of DSP- and LUT-based GEneral Matrix-Multiplication (GEMM) computing cores, which forms the entire computing system in a heterogeneous fashion. The DSP- and LUT-based GEMM cores are computed w.r.t a unified Instruction Set Architecture (ISA) and unified buffers. Along the data flow of the neural network inference path, the computation of the convolution/fully-connected layer is split into two portions, handled by the DSP- and LUT-based GEMM cores asynchronously. From the software perspective, we mathematically and systematically model the latency and resource utilization of the proposed heterogeneous accelerator, regarding varying system design configurations. Through leveraging the reinforcement learning technique, we construct a framework to achieve end-to-end selection and optimization of the design specification of target heterogeneous accelerator, including workload split strategy, mixed-precision quantization scheme, and resource allocation of DSP- and LUT-core. In virtue of the proposed design framework and heterogeneous computing system, our design outperforms the state-of-the-art Mix & Match design with latency reduced by 1.12-1.32× with higher inference accuracy. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs 22

HeteroFlow: An Accelerator Programming Model with Decoupled ...

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Xiang, Shaojie Lai, Yi-Hsiang Zhou, Yuan Chen, Hongzheng Zhang, Niansong Pal, Debjit Zhang, Zhiru School of Electrical and Computer Engineering Cornell University IthacaMI United States

ISBN: (纸本)9781450391498

To achieve high performance with FPGA-equipped heterogeneous compute systems, it is crucial to co-optimize data placement and compute scheduling to maximize data reuse and bandwidth utilization for both on- and off-chip memory accesses. However, optimizing the data placement for FPGA accelerators is a complex task. One must acquire in-depth knowledge of the target FPGA device and its associated memory system in order to apply a set of advanced optimizations. Even with the latest high-level synthesis (HLS) tools, programmers often have to insert many low-level vendor-specific pragmas and substantially restructure the algorithmic code so that the right data are accessed at the right loop level using the right communication schemes. These code changes can significantly compromise the composability and portability of the original program. To address these challenges, we propose HeteroFlow, an FPGA accelerator programming model that decouples the algorithm specification from optimizations related to orchestrating the placement of data across a customized memory hierarchy. Specifically, we introduce a new primitive named .to(), which provides a unified programming interface for specifying data placement optimizations at different levels of granularity: (1) coarse-grained data placement between host and accelerator, (2) medium-grained kernel-level data placement within an accelerator, and (3) fine-grained data placement within a kernel. We build HeteroFlow on top of the open-source HeteroCL DSL and compilation framework. Experimental results on a set of realistic benchmarks show that, programs written in HeteroFlow can match the performance of extensively optimized manual HLS design with much fewer lines of code. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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HP-GNN: Generating High Throughput GNN Training Implementation on CPU-FPGA Heterogeneous Platform 22

HP-GNN: Generating High Throughput GNN Training Implementati...

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Lin, Yi-Chien Zhang, Bingyi Prasanna, Viktor Lin, Yi-Chien University of Southern California Los AngelesCA United States

ISBN: (纸本)9781450391498

Graph Neural Networks (GNNs) have shown great success in many applications such as recommendation systems, molecular property prediction, traffic prediction, etc. Recently, CPU-FPGA heterogeneous platforms have been used to accelerate many applications by exploiting customizable data path and abundant user-controllable on-chip memory resources of FPGAs. Yet, accelerating and deploying GNN training on such platforms requires not only expertise in hardware design but also substantial development efforts. We propose HP-GNN, a novel framework that generates high throughput GNN training implementations on a given CPU-FPGA platform that can benefit both application developers and machine learning researchers. HP-GNN takes GNN training algorithms, GNN models as the inputs, and automatically performs hardware mapping onto the target CPU-FPGA platform. HP-GNN consists of: (1) data layout and internal representation that reduce the memory traffic and random memory accesses;(2) optimized hardware templates that support various GNN models;(3) a design space exploration engine for automatic hardware mapping;(4) high-level application programming interfaces (APIs) that allow users to specify GNN training with only a handful of lines of code. To evaluate HP-GNN, we experiment with two well-known sampling-based GNN training algorithms and two GNN models. For each training algorithm and model, HP-GNN generates implementation on a state-of-the-art CPU-FPGA platform. Compared with CPU-only and CPU-GPU platforms, experimental results show that the generated implementations achieve 55.67x and 2.17x speedup on the average, respectively. Compared with the state-of-the-art GNN training implementations, HP-GNN achieves up to 4.45x speedup. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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