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检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 609 条记录，以下是431-440 订阅

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An embedded true random number generator for FPGAs

An embedded true random number generator for FPGAs

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Kohlbrenner, Paul Gaj, Kris Lockheed Martin 3201 Jermantown Road Fairfax VA 22030 United States George Mason University 4400 University Drive Fairfax VA 22030 United States

field programmable gate arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had less than optimal choices for a source of truly random bits. In this paper we extend a technique that uses on-chip jitter and PLLs to a much larger class of FPGAs that do not contain PLLs. Our design uses only the Configurable Logic Blocks (CLBs) common to all FPGAs, and has a self-testing capability. Using the intrinsic jitter contained in digital circuits, we produce random bits at speeds of up to 0.5 Mbits/second with good statistical characteristics. We discuss the engineering challenges of extracting random bits from digital circuits, and we report the results of running standard statistical tests (NIST) on the output generated by our system.

关键词： field programmable gate arrays

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Exploration of pipelined FPGA interconnect structures

Exploration of pipelined FPGA interconnect structures

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Sharma, Akshay Compton, Katherine Ebeling, Carl Hauck, Scott Electrical Engineering University of Washington Seattle WA United States Electrical and Computer Engineering Northwestern University Evanston IL United States Computer Science and Engineering University of Washington Seattle WA United States

In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of registered routing track segments, registered 10 terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined FPGA. Our experiments with the RaPiD architecture identify tradeoffs that must be made while designing the interconnect structure of a pipelined FPGA. The post-exploration architecture that we found shows a 19% improvement over RaPiD, while the area overhead incurred in placing and routing benchmarks netlists on the post-exploration architecture is 18%.

关键词： field programmable gate arrays

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Low-power technology mapping for FPGA architectures with dual supply voltages

Low-power technology mapping for FPGA architectures with dua...

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Chen, Deming Cong, Jason Li, Fei He, Lei Computer Science Department University of California Los Angeles United States Electrical Engineering Department University of California Los Angeles United States

In this paper we study the technology mapping problem of FPGA architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. We first design a single-Vdd mapping algorithm that achieves better power results than the latest published low-power mapping algorithms. We then show that our dual-Vdd mapping algorithm can further improve power savings by up to 11.6% over the single-Vdd mapper. In addition, we investigate the best low-Vdd/high-Vdd ratio for the largest power reduction among several dual-Vdd combinations. To our knowledge, this is the first work on dual-Vdd mapping for FPGA architectures.

关键词： field programmable gate arrays

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Highly pipelined asynchronous FPGAs

Highly pipelined asynchronous FPGAs

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Teifel, John Manohar, Rajit Computer Systems Laboratory Cornell University Ithaca NY 14853 United States

We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and show how asynchronous logic can efficiently take advantage of this large amount of pipelining. Our FPGA, which does not use a clock to sequence computations, automatically "self-pipelines" its logic without the designer needing to be explicitly aware of all pipelining details. This property makes our FPGA ideal for throughput-intensive applications and we require minimal place and route support to achieve good performance. Benchmark circuits taken from both the asynchronous and clocked design communities yield throughputs in the neighborhood of 300-400 MHz in a TSMC 0.25μm process and 500-700 MHz in a TSMC 0.18μm process.

关键词： field programmable gate arrays

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Making visible the thermal behaviour of embedded microprocessors on FPGAs. A progress report

Making visible the thermal behaviour of embedded microproces...

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acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Lopez-Buedo, Sergio Boemo, Eduardo Computer Engineering Department School of Engineering Universidad Autonoma de Madrid Spain

This paper shows a method to verifying the thermal status of complex FPGA-based circuits like microprocessors. Thus, the designer can evaluate if a particular block is working beyond specifications. The idea is to extract the output frequencies of an array of ring-oscillators previously distributed in the die, taking full advantage of the configuration port capabilities in Xilinx technology. As a result, it is shown that the FPGA technology offers the designers of embedded systems the possibility of viewing a detailed thermal map of a circuit at a minimum cost. The verification can be done in actual working conditions;for example with heat sinks and fans attached to the chip, inside the system case, or even in an on-board satellite application. The main results of the work are unthinkable using other alternatives like IR cameras, external sensors, or embedded diodes.

关键词： field programmable gate arrays

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Incremental physical resynthesis for timing optimization

Incremental physical resynthesis for timing optimization

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Suaris, Peter Liu, Lungtien Ding, Yuzheng Chou, Nanchi Mentor Graphics Corporation 8005 Boeckman Road Wilsonville OR 97070 United States

This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and physical optimizations without incurring unmanageable runtime complexity. Unlike previous approaches to this problem which limit the types of operations and/or architectural features, we take advantage of many architectural characteristics of modern FPGA devices, and utilize many types of optimizations including cell repacking, signal rerouting, resource retargeting, and logic restructuring, accompanied by efficient incremental placement, to gradually transform a design via a series of localized logic and physical optimizations that verifiably improve overall compliance with timing constraints. This procedure works well on small and large designs, and can be administered through either an automatic optimizer, or an interactive user interface. Our preliminary experiments showed that this approach is very effective in fixing or reducing timing violations that cannot be reduced by other optimization techniques: For a set of test cases to which this is applicable, the worst timing violation is reduced by an average of 42.8%.

关键词： field programmable gate arrays

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Active leakage power optimization for FPGAs

Active leakage power optimization for FPGAs

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Anderson, Jason H. Najm, Farid N. Tuan, Tim ECE Department University of Toronto Toronto Ont. Canada Xilinx Toronto Development Centre Toronto Ont. Canada Xilinx Research Labs San Jose CA United States

We consider active leakage power dissipation in FPGAs and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a fundamental property of basic FPGA logic elements (look-up-tables) that allows a logic signal in an FPGA design to be interchanged with its complemented form without any area or delay penalty. We apply this property to select polarities for logic signals so that FPGA hardware structures spend the majority of time in low leakage states. In an experimental study, we optimize active leakage power in circuits mapped into a state-of-the-art 90nm commercial FPGA. Results show that the proposed approach reduces active leak-age by 25%, on average.

关键词： field programmable gate arrays

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Nanowire-based sublithographic programmable logic arrays

Nanowire-based sublithographic programmable logic arrays

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acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： DeHon, André Wilson, Michael J. Dept. of CS 256-80 California Institute of Technology Pasadena CA 91125 United States

How can programmable Logic arrays (PLAs) be built without relying on lithography to pattern their smallest features? In this paper, we detail designs which exploit emerging, bottom-up material synthesis techniques to build PLAs using molecular-scale nanowires. Our new designs accommodate technologies where the only post-fabrication programmable element is a non-restoring diode. We introduce stochastic techniques which allow us to restore the diode logic at the nanoscale so that it can be cascaded and interconnected for general logic evaluation. Under conservative assumptions using 10nm nanowires and 90nm lithographic support, we project yielded logic density around 500,000nm 2/OR term for a 60 OR-term array;a complete 60-term, two-level PLA is roughly the same size as a single 4-LUT logic block in 22nm lithography. Each OR term is comparable in area to a 4-transistor hardwired gate at 22nm. Mapping sample datapaths and conventional programmable logic benchmarks, we estimate that each 60-OR-term PLA plane will provide equivalent logic to 5-10 4-input LUTs.

关键词： Logic circuits

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A reconfigurable unit for a clustered programmable-reconfigurable processor

A reconfigurable unit for a clustered programmable-reconfigu...

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acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Kujoth, Richard B. Wang, Chi-Wei Gottlieb, Derek B. Cook, Jeffrey J. Carter, Nicholas P. Department of Electrical Engineering Univ. Illinois at Urbana-Champaign Urbana IL 61801 United States

In a clustered programmable-reconfigurable processor, multiple programmable processors and blocks of reconfigurable logic communicate through a register-based communication mechanism, which reduces the impact of wire delay on clock cycle time. In this paper, we present a circuit-level design for the reconfigurable clusters used on the Amalgam programmable-reconfigurable processor. We outline our interleaved reconfigurable array design, which provides high bandwidth to and from the register file without requiring large amounts of register control logic. We characterize the latency of operations in our array, and present results that show the impact that this latency has on overall system performance in a range of fabrication processes. Finally, we present a pipelining scheme that enables the array to operate at clock rates closer to those of programmable processors and allows for better scaling in future technologies.

关键词： Program processors

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The SFRA: A corner-turn FPGA architecture

The SFRA: A corner-turn FPGA architecture

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acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Weaver, Nicholas Hauser, John Wawrzynek, John CS Department UC Berkeley Berkeley CA Intl. Computer Science Institute

FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better to employ fixed-frequency FPGAs operating at a high clock frequency. Such fixed-frequency arrays require pipelined interconnect structures, which are difficult to support in a traditional FPGA architecture. We have developed a novel approach, called a "corner-turn" interconnect, based on a Manhattan array of logically depopulated S-boxes with full connectivity but limited routability. This interconnect supports new polynomial-time routing techniques while maintaining conventional placement and other upstream toolflow. We have used the corner-turn interconnect to define a fixed-frequency FPGA architecture, the SFRA, that is largely compatible with the Xilinx Virtex while providing higher speed, pipelined operation. Our tools automatically repipeline designs to operate at the SFRA's intrinsic clock frequency. Since the arrays are largely compatible, we directly compare the SFRA with the Virtex on four benchmark designs. On these benchmarks, the SFRA offers higher throughput and competitive throughput per area. The SFRA routing and retiming tools also run one to two orders of magnitude faster than their Xilinx counterparts.

关键词： field programmable gate arrays

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