In this work we investigate the architecture of a Via Patterned gate Array (VPGA) [1], focusing primarily on: 1) the optimal lookup table (LUT) size;and 2) a comparison the crossbar and switch block routing architectu...
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ISBN:
(纸本)9781581136500
In this work we investigate the architecture of a Via Patterned gate Array (VPGA) [1], focusing primarily on: 1) the optimal lookup table (LUT) size;and 2) a comparison the crossbar and switch block routing architectures. Unlike FPGAs, the routing architectures in a VPGA do not dominate the total area of the circuit. Therefore our results suggest that using smaller LUTs results in a much faster and smaller design. In the routing architecture comparison, our results also show that the switch block architecture is inferior to the crossbar architecture in terms of area utilization. As the number of routing tracks grows, the switch block architecture begins to dominate the total area of the design as in the case of the FPGAs.
The ever-growing capacity and speed of FPGAs have brought them into the heart of the silicon mainstream. Major ASIC vendors have responded by reviving masterslice gatearrays, standard prefab die with design-specific ...
ISBN:
(纸本)9781581136517
The ever-growing capacity and speed of FPGAs have brought them into the heart of the silicon mainstream. Major ASIC vendors have responded by reviving masterslice gatearrays, standard prefab die with design-specific metal layers. They claim lower NREs, quicker delivery and easier design than cell-based ASICs, and lower unit cost, better speed, capacity and power than *** these gatearrays spell doom for FPGA vendors' dreams of displacing the ASIC as a mainstream silicon platform?Will the FPGA's high volume, superior flexibility and time-to-market prevail?Will FPGA's co-exist in different classes of application?A panel of experts from FPGA and ASIC vendors and academia will duke it out. Each panelist will give a short presentation putting forward their point of view followed by an interactive debate among the panelists and attendees.
The proceddings contains 24 papers from international syposium on fieldprogrammablegatearrays. Some of the topics discussed include: timing driven placement for hierarchical programmable logic devices;performance d...
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The proceddings contains 24 papers from international syposium on fieldprogrammablegatearrays. Some of the topics discussed include: timing driven placement for hierarchical programmable logic devices;performance driven mapping for CPLD architectures;detailed routing arhitectures for embeembedded programmable logic IP cores;Microprocessor and applification specific integrated circuits;the effect of reconfigurable units in superscalar processors;run-time defect tolerance using Jbits;fpga implementation of a novel, fast motin estimation algorithm for real video compression.
The proceedings contains 26 papers from the FPGA 2002 Tenth acminternationalsymposium on field-programmablegatearrays. Topics discussed include: interconnect enhancements for a high-speed PLD architecture;FPGA swi...
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The proceedings contains 26 papers from the FPGA 2002 Tenth acminternationalsymposium on field-programmablegatearrays. Topics discussed include: interconnect enhancements for a high-speed PLD architecture;FPGA switch block layout and evaluation;a faster distributed arithmetic architecture for FPGAs;efficient circuit clustering for area and power reduction in FPGAs and integrated retiming and placement for fieldprogrammablegatearrays.
This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on FPGA (fieldprogrammablegate Array). Some new architectures are presented,...
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ISBN:
(纸本)9781581134520
This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on FPGA (fieldprogrammablegate Array). Some new architectures are presented, including a pipelined architecture exploiting the maximum carry chain length of the FPGA which is used to implement the modular exponentiation operation required for RSA encryption and decryption. Speed and area comparisons are performed on the optimised designs. The issues of targeting a design specifically for a reconfigurable device are considered, taking into account the underlying architecture imposed by the target technology.
As programmable logic grows more viable for implementing full design systems, performance has become a primary issue for programmable logic device architectures. This paper presents the high-level design of Dali, a PL...
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ISBN:
(纸本)9781581134520
As programmable logic grows more viable for implementing full design systems, performance has become a primary issue for programmable logic device architectures. This paper presents the high-level design of Dali, a PLD architecture specifically aimed at performance-driven applications. We will present significant portions of the background research that contributed to our architectural decisions, an overview of the core routing architecture and benchmarking experiments used to evaluate the prototype device.
As device densities increase, testing cost is becoming a larger portion of the overall FPGA manufacturing cost. We present an approach to speed up testing FPGA interconnect by reconfiguring it during the test. Simple ...
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ISBN:
(纸本)9781581134520
As device densities increase, testing cost is becoming a larger portion of the overall FPGA manufacturing cost. We present an approach to speed up testing FPGA interconnect by reconfiguring it during the test. Simple additions are made to create feedback shift register structures, which considerably reduce the number of test configurations for the switching matrix interconnect. This new testing architecture reduces switching matrix test time by 66% and the diagnosis time by 72%. The additions are transparent to the users both in terms of speed and functionality.
Random number generators (RNGs) based upon neighborhood-of-four cellular automata (CA) with asymmetrical, non-local connections are explored. A number of RNGs that pass Marsaglia's rigorous Diehard suite of random...
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ISBN:
(纸本)9781581134520
Random number generators (RNGs) based upon neighborhood-of-four cellular automata (CA) with asymmetrical, non-local connections are explored. A number of RNGs that pass Marsaglia's rigorous Diehard suite of random number tests have been discovered. A neighborhood size of four allows a single CA cell to be implemented with a four-input lookup table and a one-bit register which are common building blocks in popular fieldprogrammablegatearrays (FPGAs). The investigated networks all had periodic (wrap around) boundary conditions with either 1-d, 2-d, or 3-d interconnection topologies. Trial designs of 64-bit networks using a Xilinx XCV 1000-6 FPGA predict a maximum clock rate of 214 MHz to 230 MHz depending upon interconnection topology.
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