This paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with per...
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ISBN:
(纸本)9780897919784
This paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar to that of a custom ASIC design, while allowing all of the basic FIR design parameters, including coefficient precision, to be configured. Previous research has already shown that FPGAs can provide a high-performance alternative to DSP processors. Experimental comparisons in this paper show that the performance and area efficiency of the proposed architecture is similar to that of custom approaches across a wide range of filter sizes and configurations.
It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, th...
ISBN:
(纸本)9780897919784
It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for customers that do not use all of the storage provided. This chip area need not be wasted, and can in fact be used very efficiently, if the arrays are configured as large multi-output ROMs, and used to implement *** order to efficiently use the embedded arrays in this way, a technology mapping algorithm that identifies parts of circuits that can be efficiently mapped to an embedded array is required. In this paper, we describe such an algorithm. The new tool, called SMAP, packs as much circuit information as possible into the available memory arrays, and maps the rest of the circuit into four-input lookup-tables. On a set of 29 sequential and combinational benchmarks, the tool is able to map, on average, 60 4-LUTs into a single 2-Kbit memory array. If there are 16 arrays available, it can map, on average, 358 4-LUTs to the 16 arrays.
In the development of new FPGA architectures, a designer must balance speed, density and routing flexibility. In this paper, we discuss a new FPGA architecture based on a patented [1], novel, segmented routing fabric ...
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ISBN:
(纸本)9780897919784
In the development of new FPGA architectures, a designer must balance speed, density and routing flexibility. In this paper, we discuss a new FPGA architecture based on a patented [1], novel, segmented routing fabric that is targeted to high performance and predictability but does not sacrifice routability or area efficiency. Current segmented architectures allow much flexibility in routing, but incur large delay penalties when a signal has high fanout or must traverse medium to long distances to reach its target. Reducing the number of programmable interconnect points (PIPs) that a signal must traverse to reach its target, while eliminating the RC delay buildup due to signal fanout, improves design performance and offers highly predictable signal delays.
The proceedings contains 22 papers from the 1997 internationalsymposium on fieldprogrammablegatearrays. Topics discussed include: fieldprogrammablegate array (FPGA) architectures;FPGA partitioning and synthesis;...
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The proceedings contains 22 papers from the 1997 internationalsymposium on fieldprogrammablegatearrays. Topics discussed include: fieldprogrammablegate array (FPGA) architectures;FPGA partitioning and synthesis;rapid prototyping and emulation;reconfigurable computing;and FPGA floorplanning and routing.
This paper shows that the speed of FPGAs with large embedded memory arrays can be improved by adding direct programmable connections between the memories. Nets that connect to multiple memory arrays are often difficul...
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ISBN:
(纸本)9780897918015
This paper shows that the speed of FPGAs with large embedded memory arrays can be improved by adding direct programmable connections between the memories. Nets that connect to multiple memory arrays are often difficult to route, and are often part of the critical path of circuit implementations. The memory-to-memory connection structure proposed in this paper allows for the efficient implementation of these nets, resulting in a reduction in memory access time of up to 25% and a slight improvement in routability.
A circuit design for a fieldprogrammable Analog Array is presented which improves accuracy and repeatability compared to previous designs. Controlled by a configuration register, continuous-time signals are routed am...
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A circuit design for a fieldprogrammable Analog Array is presented which improves accuracy and repeatability compared to previous designs. Controlled by a configuration register, continuous-time signals are routed among programmable analog blocks to implement the user's chosen circuit. The configurable connections are realized by CMOS switches and a new innovation is that these are either buffered or nulled to cancel parasitic error. The function blocks are Op-Amps combined with passive networks which allow programmable transfer functions with accuracy insensitive to variations in process parameters and environment. The intended application area is the rapid development of analog circuits which are presently prototyped by PCBs stuffed with Op-Amp and passive components. The concept has been demonstrated on a CMOS IC and the resulting performance shows the feasibility of this approach to general purpose FPAA technology.
This paper describes the architectural configuration of the Electrically programmable Analog Circuit (EPAC), an expert cell approach to meeting the market need for an analog counterpart to the digital FPGA. It provide...
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This paper describes the architectural configuration of the Electrically programmable Analog Circuit (EPAC), an expert cell approach to meeting the market need for an analog counterpart to the digital FPGA. It provides an overview of the technology and describes the internal operation of the first commercial EPAC devices.
This paper deals with the diagnosis of fieldprogrammable interconnect systems (FPIS) in which nets are connected through programmable switches arranged in grids. A hierarchical approach to diagnosis is proposed. The ...
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This paper deals with the diagnosis of fieldprogrammable interconnect systems (FPIS) in which nets are connected through programmable switches arranged in grids. A hierarchical approach to diagnosis is proposed. The conditions by which such process yields full diagnosis and the characteristics of the programming sequence, are fully proved. For a FPIS consisting of a k × k grid array, the number of tests is given by 4 + 4kn2, while the number of programming steps is 4nk + 1, where n is the dimension of a grid. The application of this technique to commercially available FPIS in FPGAs, is discussed.
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