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检索条件"任意字段=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 608 条记录，以下是81-90 订阅

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An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops 20

An Algorithm for Delay Optimal Logic Replication for FPGAs A...

引用

proceedings of the 2020 acm/sigda international symposium on field-programmable gate arrays

作者： Rupesh S. Shelar Synopsys Inc. Hillsboro OR USA

ISBN: (纸本)9781450370998

Logic replication is often necessary to improve speed of emulation for systems employing field programmable gate arrays (FPGAs), since design sizes are large enough requiring partitioning to fit a design into multiple (boards of) FPGAs. In this paper, we propose a polynomial time algorithm for combinational logic replication that ensures delay optimality for directed acyclic graphs and reduces overhead due to look-up table (LUT) and cut resources. The algorithm is further extended to consider combinational loops, often yielding delay optimal results. Experimental results on industrial designs show, on an average, 44%, 33%, and 33% reduction in overhead due to cut, LUT costs, and runtimes, respectively, compared to existing heuristics, thus demonstrating the efficiency of the algorithm.

关键词： dynamic programming optimization prototyping field programmable gate arrays (fpgas) timing combinational loops logic replication emulation algorithm

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Classifying Computations on Multi-Tenant FPGAs 21

Classifying Computations on Multi-Tenant FPGAs

引用

The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Mustafa Gobulukoglu Colin Drewes Bill Hunter Dustin Richmond Ryan Kastner University of California San Diego San Diego CA USA Georgia Tech Research Institute Atlanta GA USA University of Washington Seattle WA USA

ISBN: (纸本)9781450382182

Modern data centers leverage large FPGAs to provide low latency, high throughput, and low energy computation. FPGA multi-tenancy is an attractive option to maximize utilization, yet it opens the door to unique security threats. In this work, we develop a remote classification pipeline that targets the confidentiality of multi-tenant cloud FPGA environments. We design a unique Dual-Edged voltage fluctuation sensor that measures subtle changes in the power distribution network caused by co-located computations. The sensor measurements are given to a classification pipeline that is able to deduce information about co-located applications including the type of computation and its implementation. We study the importance of the trace length, signal conditioning algorithms, and other aspects that affect classification accuracy. Our results show that we can determine if another co-tenant is present with 96% accuracy. We can classify with 98% accuracy whether a power waster circuit is operating. Furthermore, we are able to determine if a cryptographic operation is occurring, differentiate between different cryptographic algorithms (AES and PRESENT) and microarchitectural implementations (Microblaze, ORCA, and PicoRV32).

关键词： programmable logic sensor hardware security power distribution network side-channel analysis neural network multi-tenant FPGA

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A Multiplication-Free FPGA Implementation of Multiple RLWE Encryption using Anti-Circulant Matrix 16

A Multiplication-Free FPGA Implementation of Multiple RLWE E...

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16th IEEE international Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Yang, Chen Zhang, Fahong Wang, Jianfei Su, Yang Xi'an Jiaotong University School of Microelectronics Shaanxi Xi'an710049 China Engineering University of Pap School of Cryptography Engineering Shaanxi Xi'an710086 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

With the expansion of cloud services and privacy security becomes more crucial, fully homomorphic encryption (FHE) scheme which operates data in ciphertext domain has been widely concerned. Lattice-based cryptography ring learning with errors (RLWE), together with its variants RLWE' and RGSW, form the core component of main-stream homomorphic encryption schemes. This paper presents a universal RLWE encryption module supports ciphertext generation of three cryptographic schemes above. The design uses anti-circulant matrix to convert polynomial multiplication to N-level inner product between vector and anti-circulant matrix to wipe off additional modular reduction. Meanwhile, Montgomery reduction is used to realize multiplicationfree polynomial multiplication. The results show that the utilizations of LUT and FF are reduced by 51% and 30% respectively, as well as completely avoiding DSP usage. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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MLBlocks: FPGA Blocks for Machine Learning Applications 21

MLBlocks: FPGA Blocks for Machine Learning Applications

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Seyedramin Rasoulinezhad David Boland Philip H.W. Leong The University of Sydney Sydney Australia

ISBN: (纸本)9781450382182

The underlying goal of FPGA architecture research is to devise flexible substrates which implement a wide variety of circuits efficiently. Contemporary FPGA architectures have been optimized to support networking, signal processing and image processing applications through high precision digital signal processing (DSP) blocks. The recent emergence of machine learning has created a new set of demands characterized by: 1) higher computational density and 2) low precision arithmetic requirements. With the goal of exploring this new design space in a methodical manner, we first propose a problem formulation involving computing nested loops over multiply-accumulate (MAC) operations, which covers many basic linear algebra primitives and standard deep neural network (DNN) layers. A quantitative methodology for deriving efficient coarse-grained compute block architectures from benchmarks is then proposed together with a family of new compute units, called MLBlocks. These blocks are flexible mesh-based systolic array units parameterized with different data movements, data reuse, and multi-precision support. They utilize a columnar arrangement which is compatible with existing FPGA architectures. Finally, using synthetic benchmarks, we demonstrate that MLBlocks offer significantly improved performance over the commercial Xilinx DSP48E2, while maintaining similar area and timing requirements to current DSPs.

关键词： FPGA architectures reconfigurable architecture neural networks digital signal processing systolic arrays coarse-grained compute blocks

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FPGA 2019 chairs’ welcome

FPGA 2019 - Proceedings of the 2019 ACM/SIGDA International ...

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FPGA 2019 - proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays 2019年 3-3页

作者： Neuendorffer, Stephen Bazargan, Kia Xilinx United States University of Minnesota United States

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FPGA-based Acceleration of Binary Neural Network Training with Minimized Off-Chip Memory Access

FPGA-based Acceleration of Binary Neural Network Training wi...

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IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Chundi, Pavan Kumar Liu, Peiye Park, Sangsu Lee, Seho Seok, Mingoo Columbia Univ Dept Elect Engn New York NY 10027 USA SK Hynix Semicond Future Memory Res San Jose CA USA

ISBN: (纸本)9781728129549

In this paper, we examine the feasibility of FPGA as a platform for training a convolutional binary-weight neural network. Training a neural network requires more data movement compared to inference. Acceleration of training on an FPGA is, therefore, a challenge because the data movement increases off-chip memory accesses. We try to address this problem by storing most of the data in the on-chip memory and adopting batch renormalization. This allows for training a large network by reducing the required intermediate data and its movement. For the case where all data except the input images can be stored on an FPGA chip, we present an accelerator for training CNNs to classify the CIFAR-10 dataset. Further, we study the impact of network size on performance and energy of FPGA and GPU. Our accelerator mapped in the Arria 10 FPGA chip obtains up-to 9.33X higher energy efficiency compared to the Nvidia Geforce GTX 1080 Ti GPU at similar performance.

关键词： Training Neural networks field programmable gate arrays Backpropagation Convolutional codes Acceleration Convolution

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HDL FSM Code Generation Using a MIPS-based Assembler 28

HDL FSM Code Generation Using a MIPS-based Assembler

引用

28th IEEE international symposium on Industrial Electronics (IEEE-ISIE)

作者： Meyer, Dominik Eckert, Marcel Klauer, Bernd Haase, Jan Helmut Schmidt Univ Hamburg Fac Elect Engn Comp Engn Hamburg Germany Univ Lubeck Inst Comp Engn Lubeck Germany

ISBN: (纸本)9781728136660

The implementation of Finite State Machines (FSMs) is a recurring task in the development of embedded systems when field programmable gate arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) are being designed. The standard implementation language for these FSMs in this context is a Hardware Description Language (HDL) like VHDL or Verilog. The implementation complexity can rise quickly depending on FSM size and which devices/components are controlled. In many cases FSMs enforce sequential execution of instructions in the concurrent world of FPGAs or ASICs. This paper proposes the use of a MIPS-based assembly dialect and assembler called aFSM to decrease the implementation complexity of such FSMs by automatically generating the FSMs VHDL code. A human VHDL implementation of an Ethernet controller with an FPGA is compared against the implementation with aFSM to evaluate the assembler.

关键词： VHDL field programmable gate arrays Clocks Protocols Ethernet Microprocessors

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FPGA Processing Path Calibration For Truncation Errors Reduction 20

FPGA Processing Path Calibration For Truncation Errors Reduc...

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20th international Radar symposium (IRS)

作者： Kniola, Michal Kawalec, Adam Mil Univ Technol Fac Elect Inst Radioelect Gen Witold Urbanowicz Str 2 PL-00908 Warsaw Poland

ISBN: (纸本)9783736998605

Results of research carried out on a FPGA-implemented matched filter are presented in this paper. Influence of MSB and LSB (Most Significant Bits and Least Significant Bits) truncations on the output signal waveform was analyzed Purpose of the work was to devise a practical approach or implementation methodology in order to increase in efficiency of available bus width utilization.

关键词： field programmable gate arrays Matched filters Radar Calibration Signal processing algorithms Filtration Data buses"

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Unleashing the Power of FPGAs as programmable Switches 20

Unleashing the Power of FPGAs as Programmable Switches

引用

proceedings of the 2020 acm/sigda international symposium on field-programmable gate arrays

作者： Thomas Luinaud Thibaut Stimpfling Jeferson Santiago Da Silva Yvon Savaria J.M. Pierre Langlois Polytechnique Montréal Montréal PQ Canada Polytechnique Montréal Montreal PQ Canada Polytechnique Montréal Montréal Canada

ISBN: (纸本)9781450370998

The P4 language and the PISA architecture have revolutionized the field of networking. Thanks to P4 and PISA, new networking applications and protocols can be rapidly evaluated on high performance switches. While P4 allows the expression of a wide range of packet processing algorithms, current programmable switch architecture limit the overall processing flexibility. To address this shortcoming recent work have proposed to implement PISA on FPGAs. However, little effort has been devoted to analyze whether FPGAs are good candidates to implement PISA. In this work, we take a step back and evaluate the micro-architecture efficiency of various PISA blocks. Using a theoretical analysis and experiments, we demonstrate that current FPGA architecture drastically limit the performance of a few PISA blocks. Thus, we explore two avenues to alleviate these shortcomings. First, we identify some network applications that are well tailored to current FPGAs. Second, to support a wider range of networking applications, we propose modifications to the FPGA architecture which can also be of interest outside the networking field.

关键词： data plane network p4

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Development of a Low Cost 15-Gsps Analog-to-Digital Converter Board by using a field programmable gate Array Mezzanine Card Connector for FPGA-Based Backends 28

Development of a Low Cost 15-Gsps Analog-to-Digital Converte...

引用

28th IEEE international symposium on Industrial Electronics (IEEE-ISIE)

作者： Jiang, Homin Yw, Chen-Yu Chen, Mark Liu, Miter ASIAA Taipei Taiwan E Element Inc Taipei Taiwan

ISBN: (纸本)9781728136660

We designed and fabricated a 4-bit, 15-gigasamples-per-second (Gsps) analog-to-digital converter (ADC) printed circuit board assembly (PCBA). An Adsantec ANST7122-KMA flash ADC chip was used. The developed PCBA provides data acquisition systems with a wide bandwidth, provides an analog bandwidth of up to 10 GHz (3 dB loss), and enables a chip on the board to exhibit an analog bandwidth of up to 20 GHz. The PCBA is equipped with a field-programmable gate array (FPGA) Mezzanine Card (FMC) connector;this type of connector is gaining prominence in the industry. We developed interface code for using a Xilinx KCU105 and VCU118 evaluation boards. A novel channel bonding method has been developed for alignment of the high-speed serial data input. Effective number of bits (ENOB) and signal to noise and distortion (SINAD) characteristics has been examined quickly following the IEEE standard at the sampling rates of 10.0, 12.8 and 13.6 Gsps respectively. The preliminary ENOB are in the range of 3.5-3.9/2.2-2.8/*** respectively, and SINAD are in the range of 22-25/16-19/16-19 respectively.

关键词： Clocks field programmable gate arrays Connectors Bonding Bandwidth Phase locked loops Telescopes

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