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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Quantifying the cost and benefit of latency insensitive communication on FPGAs 14

Quantifying the cost and benefit of latency insensitive comm...

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Murray, Kevin E. Betz, Vaughn Dept. of Electrical and Computer Engineering University of Toronto Ontario Canada

ISBN: (纸本)9781450326711

Latency insensitive communication oers many potential benets for FPGA designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to understand the costs and trade-os associated with any new design style. This paper presents optimized implementations of latency insensitive communication building blocks, quanties their overheads in terms of area and frequency, and provides guidance to designers on how to generate high-speed and areae cient latency insensitive systems.

关键词： field programmable gate arrays (FPGA)

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FPGA Acceleration for Computational Glass-Free Displays 17

FPGA Acceleration for Computational Glass-Free Displays

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acm/sigda international symposium on field-programmable gate arrays

作者： He, Zhuolun Luo, Guojie Peking Univ Sch EECS Ctr Energy Efficient Comp & Applicat Beijing Peoples R China NUDT Collaborat Innovat Ctr High Performance Comp Changsha Hunan Peoples R China PKU UCLA Joint Res Inst Sci & Engn Beijing Peoples R China

ISBN: (纸本)9781450343541

The increasing computational power enables various new applications that are runtime prohibitive before. FPGA is one of such computational power with both reconfigurability and energy efficiency. In this paper, we demonstrate the feasibility of eyeglasses-free displays through FPGA acceleration. Specifically, we propose several techniques to accelerate the sparse matrix-vector multiplication and the L-BFGS iterative optimization algorithm with the consideration of the characteristics of FPGAs. The experimental results show that we reach a 12.78X overall speedup of the glass-free display application.

关键词： fpga accelerator l-bfgs algorithm sparse matrix-vector multiplication light field display

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Location, location, location - The role of spatial locality in asymptotic energy minimization 13

Location, location, location - The role of spatial locality ...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： DeHon, André M. Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450318877

Locality exploitation is essential to asymptotic energy minimization for gate array netlist evaluation. Naive implementations that ignore locality, including flat crossbars and simple processors based on monolithic memories, can require O(N2) energy for an N node graph. Specifically, it is important to exploit locality (1) to reduce the size of the description of the graph, (2) to reduce data movement, and (3) to reduce instruction movement. FPGAs exploit all three. FPGAs with a Rent Exponent p © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Managing pipeline-reconfigurable FPGAs 98

Managing pipeline-reconfigurable FPGAs

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Cadambi, Srihari Weener, Jeffrey Goldstein, Seth Copen Schmit, Herman Thomas, Donald E. Carnegie Mellon Univ Pittsburgh PA United States

ISBN: (纸本)9780897919784

While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using a combination of pipeline reconfiguration and run-time scheduling of both configuration streams and data streams. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis predicts that PipeRench will outperform commercial FPGAs and DSPs in both overall performance and in performance per mm2.

关键词： field programmable gate arrays

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Partitioning sequential circuits on dynamically reconfigurable FPGAs

Partitioning sequential circuits on dynamically reconfigurab...

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Chang, Douglas Marek-Sadowska, Malgorzata Univ of California Santa Barbara Santa Barbara United States

A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and interconnect is time-multiplexed. Thus for a circuit to be implemented on a DRFPGA, it needs to be partitioned such that each subcircuit can be executed at a different time. In this paper, the partitioning of sequential circuits for execution on a DRFPGA is studied. To determine how to correctly partition a sequential circuit, and what are the costs in doing so, we propose a new gate-level model that handles time-multiplexed computation. We also introduce an enhanced force directed scheduling (FDS) algorithm to partition sequential circuits that finds a correct partition with low logic and communication costs, under the assumption that maximum performance is desired. We use our algorithm to partition seven large ISC AS'89 sequential benchmark circuits. The experimental results show that the enhanced FDS reduces communication costs by 27.5% with only a 1.1% increase in the gate cost compared to traditional FDS.

关键词： field programmable gate arrays

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A high performance FPGA-based implementation position specific iterated BLAST

A high performance FPGA-based implementation position specif...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Kasap, Server Benkrid, Khaled Liu, Ying University of Edinburgh United Kingdom School of Electronics and Engineering Mayfield Road Edinburgh EH9 3JL United Kingdom

ISBN: (纸本)9781605584102

We present in this paper the first reported FPGA implementation of the Position Specific Iterated BLAST (PSI-BLAST) algorithm. The latter is a heuristic biological sequence alignment algorithm that is widely used in the bioinformatics and computational biology world in order to detect weak homologs. The architecture of our FPGA implementation is parameterized in terms of sequence lengths, scoring matrix, gap penalties and cut-off and threshold values. It is composed of various blmocks each of which performs one step of the algorithm in parallel. This results in high performance implementations, which easily outperform equivalent software implementations by one order of magnitude or more. Furthermore, the core was captured in an FPGA-platformindependent language, namely the Handel-C language, to which no specific resource inference or placement constraints were applied. This makes our core portable across different FPGA families and architectures. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Magnetic tunnelling junction based FPGA 06

Magnetic tunnelling junction based FPGA

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Bruchon, Nicolas Torres, Lionel Sassatelli, Gilles Cambon, Gaston LIRMM 161 rue Ada 34392 Montpellier Cedex 5 France

ISBN: (纸本)1595932925

The aim of this paper is to propose a real time reconfigurable (RTR) micro-FPGA using new non volatile memory. Magnetic tunneling junctions (MTJ) used in Magnetic random access memories (MRAM.) are compatible with classical CMOS processes. Moreover remanent property of such a memory could limit configuration time and power consumption required at each power up of the die. Nevertheless, each configuration memory point has to be readable independently from each other, that is why the approach is different from the classical memory array one. Copyright 2006 acm.

关键词： field programmable gate arrays

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High-performance carry chains for FPGAs 98

High-performance carry chains for FPGAs

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Hauck, Scott Hosler, Matthew M. Fry, Thomas W. Northwestern Univ Evanston IL United States

ISBN: (纸本)9780897919784

Carry chains are an important consideration for most computations, including FPGAs. Current FPGAs dedicate a portion of their logic to support these demands via a simple ripple carry scheme. In this paper we demonstrate how more advanced carry constructs can be embedded into FPGAs, providing significantly higher performance carry computations. We redesign the standard ripple carry chain to reduce the number of logic levels in each cell. We also develop entirely new carry structures based on high performance adders such as Carry Select, Carry Lookahead, and Brent-Kung. Overall, these optimizations achieve a speedup in carry performance of 3.8 times over current architectures.

关键词： field programmable gate arrays

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Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper-Resistant AES on FPGA 12

Intra-Masking Dual-Rail Memory on LUT Implementation for Tam...

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20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Hoang, Anh-Tuan Fujino, Takeshi Ritsumeikan Univ Kusatsu Shiga 5258577 Japan

ISBN: (纸本)9781450311557

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This paper describes our novel masked dual-rail pre-charged memory approach, called "intra-masking dual-rail memory on LUT," and its implementation on FPGA for tamper-resistant AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and the dual-rail memory and buses are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. The design is independent of the cryptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on FPGA showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced tamper-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.

关键词： Side-Channel Attack Differential Power Analysis (DPA) Masking Dual-Rail Memory Intra-Masking Dual-Rail Memory on LUT Tamper Resistance AES field programmable gate Array (FPGA)

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An embedded true random number generator for FPGAs

An embedded true random number generator for FPGAs

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acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Kohlbrenner, Paul Gaj, Kris Lockheed Martin 3201 Jermantown Road Fairfax VA 22030 United States George Mason University 4400 University Drive Fairfax VA 22030 United States

field programmable gate arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had less than optimal choices for a source of truly random bits. In this paper we extend a technique that uses on-chip jitter and PLLs to a much larger class of FPGAs that do not contain PLLs. Our design uses only the Configurable Logic Blocks (CLBs) common to all FPGAs, and has a self-testing capability. Using the intrinsic jitter contained in digital circuits, we produce random bits at speeds of up to 0.5 Mbits/second with good statistical characteristics. We discuss the engineering challenges of extracting random bits from digital circuits, and we report the results of running standard statistical tests (NIST) on the output generated by our system.

关键词： field programmable gate arrays

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