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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 834 条记录，以下是201-210 订阅

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A Time-Division Multiplexing Ising Machine on FPGAs 2017

A Time-Division Multiplexing Ising Machine on FPGAs

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8th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Yamamoto, Kasho Huang, Weigiang Takamaeda-Yamazaki, Shinya Ikebe, Masayuki Asai, Tetsuya Motomura, Masato Hokkaido Univ Sapporo Hokkaido Japan

ISBN: (纸本)9781450353168

Annealing machines based on the Ising model which can solve combinatorial optimization problems is an emerging solution to overcome the performance limit of von Neumann architecture. However, it is difficult to solve practical combinatorial optimization problems by existing approaches of FPGA-based annealing machines, due to the small number of implementable spins. In this paper, we propose the time-division multiplexing Ising machine architecture that efficiently utilizes on-chip memory resources in an FPGA, in order to address large scale combinatorial optimization problems. The evaluation result shows that it is possible to increase the spin number by 64 times compared to the conventional annealing machine. In addition, the time-multiplxing architecture liberates a logical Ising structure representing problem constraints from the physical hardware structure on an FPGA. It provides the ability to implement more complex topologies corresponding to practical of problems on FPGAs.

关键词： field programmable gate arrays (FPGA)

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QuARK: Quality-configurable Approximate STT-MRAM Cache by Fine-grained Tuning of Reliability-Energy Knobs 22

QuARK: Quality-configurable Approximate STT-MRAM Cache by Fi...

引用

22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Monazzah, Amir Mahdi Hosseini Shoushtari, Majid Miremadi, Seyed Ghassem Rahmani, Amir M. Dutt, Nikil Sharif Univ Technol Dept Comp Engn Tehran Iran TU Wien Inst Comp Technol Vienna Austria Univ Calif Irvine Dept Comp Sci Irvine CA USA

ISBN: (纸本)9781509060238

Emerging STT-MRAM memories are promising alternatives for SRAM memories to tackle their low density and high static power consumption, but impose high energy consumption for reliable read/ write operations. However, absolute data integrity is not required for many approximate computing applications, allowing energy savings with minimal quality loss. This paper proposes QuARK, a hardware/ software approach for trading reliability of STT-MRAM caches for energy savings in the on-chip memory hierarchy of multi-and many-core systems running approximate applications. In contrast to SRAM-based cache-way-level actuators, QuARK utilizes fine-grained cache-line-level actuation knobs with different levels of reliability for individual read and write accesses which are unique to STT-MRAM and suitable for systems running multiple applications with mixed accuracy sensitivity, thus avoiding interapplication actuation interference. Our experimental results with a set of recognition, mining and synthesis (RMS) benchmarks demonstrate up to 40% energy savings over a fully-protected STT-MRAM cache, with negligible loss in the quality of the generated outputs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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An Energy-efficient and High-throughput Bitwise CNN on Sneak-path-free Digital ReRAM Crossbar 22

An Energy-efficient and High-throughput Bitwise CNN on Sneak...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ni, Leibin Liu, Zichuan Song, Wenhao Yang, J. Joshua Yu, Hao Wang, Kanwen Wang, Yuangang Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA Huawei Technol Co Ltd Data Ctr Technol Lab Shenzhen Guangdong Peoples R China

ISBN: (纸本)9781509060238

Convolutional neural network (CNN) based machine learning requires a highly parallel as weIl as low power consumption (including leakage power) hardware accelerator. In this paper, we will present a digital ReRAM cross bar based CNN accelerator that can achieve significantly higher throughput and lower power consumption than state-of-arts. The CNN is trained with binary constraints on both weights and activations such that all operations become bitwise. With further use of I-bit comparator, the bitwise CNN model can be naturally realized on a digital ReRAM-crossbar device. A novel sneak-path-free ReRAM-crossbar is further utilized for large-scale realization. Simulation experiments show that the bitwise CNN accelerator on the digital ReRAM crossbar achieves 98.3% and 91. 4% accuracy on MNIST and CIFAR-IO benchmarks, respectively. Moreover, it has a peak throughput of 792GOPS at the power consumption of 6.3mW, which is 18.86 times higher throughput and 44.1 times lower power than CMOS CNN (non-binary) accelerators.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Design High Bandwidth-Density, Low Latency and Energy Efficient On-Chip Interconnect 22

Design High Bandwidth-Density, Low Latency and Energy Effici...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Wang, Yong Wu, Hui Univ Rochester Dept Elect & Comp Engn Rochester NY 14627 USA

ISBN: (纸本)9781509060238

For future high-performance computing chips, onchip interconnect requires large bandwidth-density, low latency, and high energy-efficiency, which pose significant design challenges. This paper presents a design space exploration of transmission line based on-chip interconnect. First, we conduct an optimization of on-chip transmission lines to minimize the size, channel loss and inter-symbol-interference (ISI), hence to maximize the bandwidth-density. Based on the result, differential coplanar waveguide (CPW) with 55-mu m pitch size is chosen as the transmission line topology. Next, channel capacities of channel lengths from 2 to 8 cm are characterized based on time-domain pulse responses. Various equalizers are studied, which are used to increase the ISI-limited channel capacity. To make better use of the large equalized channel capacity, pulse amplitude modulation (PAM) is employed instead of traditional non-returnto- zero (NRZ) signaling. A link budget analysis is then conducted to find the optimal modulation format for each channel. To verify our analyses, several transceivers are designed in 28-nm CMOS technology. An 84-Gb/s PAM-8 transceiver achieves 1.5Gb/ s/mu m bandwidth-density over a 4-cm channel. The unrepeated bandwidth-density is 6.1 Gb/s/mu m-cm, which is almost 10 times larger compared to prior work.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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AXSERBUS: A Quality-Configurable Approximate Serial Bus for Energy-Efficient Sensing 22

AXSERBUS: A Quality-Configurable Approximate Serial Bus for ...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Kim, Younghyun Behroozi, Setareh Raghunathan, Vijay Raghunathan, Anand Univ Wisconsin Dept Elect & Comp Engn Maison WI 53706 USA Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781509060238

Mobile, wearable, and implantable devices integrate an increasing number and variety of sensors such as microphones, image sensors, and accelerometers. These devices spend substantial amounts of time reading the sensors within them, thereby incurring significant energy dissipation over off-chip serial interconnects. This paper proposes AXSERBUS, a quality-configurable approximate serial bus that exploits the locality of sensory data and the error resiliency of sensing applications to reduce energy dissipation. AXSERBUS significantly reduces signal transitions by encoding the differentials of sensory data in three encoding modes, depending on the magnitude of the differentials: very small differentials are zeroed out, incurring no energy dissipation;intermediate differentials are encoded using special low-transition count patterns;and for high differentials, the absolute value (not the differential) of the data is transmitted. Compared to previous schemes, the proposed multi-level encoding results in more data being encoded as low-energy patterns. In addition, in the intermediate differential encoding mode, the differentials are encoded in an approximate manner, and the approximation bounds are proportional to the magnitude of the differentials. Since small differentials are more frequent than large differentials in sensory data, the proposed encoding scheme also minimizes quality degradation. We demonstrate that AXSERBUS achieves improved energy vs. quality tradeoffs compared to previous schemes. In the context of an optical character recognition (OCR) application, AXSERBUS achieves 79.4% reduction in dynamic power dissipation, while maintaining accuracy above 95%.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Approximate Memory Compression for Energy-efficiency 22

Approximate Memory Compression for Energy-efficiency

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ranjan, Ashish Raha, Arnab Raghunathan, Vijay Raghunathan, Anand Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781509060238

Memory subsystems are a major energy bottleneck in computing platforms due to frequent transfers between processors and off-chip memory. We propose approximate memory compression, a technique that leverages the intrinsic resilience of emerging workloads such as machine learning and data analytics to reduce off-chip memory traffic and energy. To realize approximate memory compression, we enhance the memory controller to be aware of memory regions that contain approximation-resilient data, and to transparently compress/decompress the data written to/read from these regions. To provide control over approximations, the quality-aware memory controller conforms to a specified error constraint for each approximate memory region. We design a software interface that programmers can use to identify data structures that are resilient to approximations. We also propose a runtime quality control framework that automatically determines the error constraints for the identified data structures such that a given target application-level quality is maintained. We evaluate our proposal by implementing a hardware prototype using the Intel UniPHY-DDR3 memory controller and NIOS-II processor, a Hynix DDR3 DRAM module, and a Stratix-IV FPGA development board. Across a suite of 8 machine learning benchmarks, approximate memory compression obtains a 1.28 x benefit in DRAM energy and a simultaneous 11.5% improvement in execution time for a small (< 1.5%) loss in output quality.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Transistor-Level Monolithic 3D Standard Cell Layout Optimization for Full-Chip Static Power Integrity 22

Transistor-Level Monolithic 3D Standard Cell Layout Optimiza...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Ku, Bon Woong Song, Taigon Nieuwoudt, Arthur Lim, Sung Kyu Georgia Inst Technol Sch ECE Atlanta GA 30332 USA Synopsys Inc Mountain View CA USA

ISBN: (纸本)9781509060238

Existing transistor-level monolithic 3D (T-M3D) standard cell layouts are based on the folding scheme, in which the pull-down network is simply folded and placed on top of the pull-up network. In this paper, we propose a new layout method, the stitching scheme, targeted towards improved cell performance and power integrity. We perform extensive analysis on each layout scheme and evaluate the timing/power benefits of the stitching scheme. Since the ground and power rails overlap in the T-M3D layouts with the folding scheme, we also present a design methodology for the power delivery network of folding T-M3D ICs to evaluate the impact of the T-M3D cell layout scheme on static power integrity. Compared to 2D ICs at iso-performance, stitching T-M3D ICs show a maximum of 6% power savings, 44% area savings with only 1% more static IR-drop in the 14nm technology node while folding T-M3D ICs undergo serious degradation in static power integrity, causing a reliability issue.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Monolithic 3D IC Designs for Low-Power Deep Neural Networks Targeting Speech Recognition 22

Monolithic 3D IC Designs for Low-Power Deep Neural Networks ...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Chang, Kyungwook Kadetotad, Deepak Cao, Yu Seo, Jae-sun Lim, Sung Kyu Georgia Inst Technol Sch ECE Atlanta GA 30332 USA Arizona State Univ Sch ECEE Tempe AZ USA

ISBN: (纸本)9781509060238

In recent years, deep learning has become widespread for various real-world recognition tasks. In addition to recognition accuracy, energy efficiency is another grand challenge to enable local intelligence in edge devices. In this paper, we investigate the adoption of monolithic 3D IC (M3D) technology for deep learning hardware design, using speech recognition as a test vehicle. M3D has recently proven to be one of the leading contenders to address the power, performance and area (PPA) scaling challenges in advanced technology nodes. Our study encompasses the influence of key parameters in DNN hardware implementations towards energy efficiency, including DNN architectural choices, underlying workloads, and tier partitioning choices in M3D. Our post-layout M3D designs, together with hardware-efficient sparse algorithms, produce power savings beyond what can be achieved using conventional 2D ICs. Experimental results show that M3D offers 22.3% iso-performance power saving, convincingly demonstrating its entitlement as a solution for DNN ASICs. We further present architectural guidelines for M3D DNNs to maximize the power saving.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Towards Flexible Automatic Generation of Graph Processing gateware 2017

Towards Flexible Automatic Generation of Graph Processing Ga...

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8th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Engelhardt, Nina So, Hayden Kwok-Hay Univ Hong Kong Dept Elect & Elect Engn Hong Kong Peoples R China

ISBN: (纸本)9781450353168

FPGAs have been demonstrated as promising platforms to accelerate graph processing applications at scale with superior energyefficiency. However, programming FPGAs is significantly more challenging than similar software solutions. To address this productivity challenge, several graph processing frameworks for FPGA have already been proposed in recent years. These frameworks aim to lower a programmeraAZs burden by requiring users to provide only logic specific to the target graph algorithm, while leaving the auto generation of the rest of the hardware design to the framework. In this work, we extend the capability of the GraVF framework and improve the scale of its supported input graphs by a) making the synchronization method independent of the network structure and b) adding support for off-chip memory. The improved system accepts graph sizes an order of magnitude larger than previously reported and provides throughput in the order of 100MTEPS per processing element.

关键词： field programmable gate arrays (FPGA)

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A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic 22

A Carbon Nanotube Transistor based RISC-V Processor using Pa...

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22nd IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Amarnath, Aporva Feng, Siying Pal, Subhankar Ajayi, Tutu Rovinski, Austin Dreslinski, Ronald G. Univ Michigan Ann Arbor MI 48109 USA

ISBN: (纸本)9781509060238

With silicon-based transistors approaching their scaling limits, multiple successor technologies are competing for silicon's place. Due to recent fabrication breakthroughs, one promising alternative is the carbon nanotube field-effect transistor (CNTFET), which uses carbon nanotubes as the channel medium instead of silicon. Although logic gates using CNTFETs have been demonstrated to provide up to an order of magnitude better energy-delay product (EDP) over siliconbased counterparts, system-level design using CNTFETs show significantly smaller EDP improvement because of the critical path of the design, output load capacitance and corresponding drive strengths of gates. In this paper, we address this challenge by exploring various architectural design choices using CNTFET-based pass transistor logic (PTL) and create an energyefficient RISC-V processor. While silicon-based design traditionally prefers complementary logic over PTL, CNTFETs are ideal candidates for PTL due to their low threshold voltage, low power dissipation, and equal strength p-type and n-type transistors. By utilizing PTL to design modules that lie on the processor's critical path, systems can efficiently exploit CNTFET's potential benefits. Our results show that while a CNTFET RISC-V processor using complementary logic achieves a 2.9. EDP improvement over a silicon design, using PTL along the critical path components in the ALU can boost EDP improvement 5x as well as reduce area by 17% over 16 nm silicon CMOS.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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