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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Towards the use of Unbundle Smart Meter for Advanced Inverters Integration 26

Towards the use of Unbundle Smart Meter for Advanced Inverte...

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26th IEEE international symposium on Industrial Electronics (ISIE)

作者： Delgado-Gomes, Vasco Martins, Joao F. Lima, Celson Borza, Paul N. NOVA Univ Lisbon Fac Sci & Technol CTS Uninova P-2829516 Caparica Portugal Fed Univ Western Para Inst Engn & Geosci UFOPA BR-68040470 Santarem Brazil Transilvania Univ Brasov Fac Elect Engn & Comp Brasov 500036 Romania

ISBN: (纸本)9781509014125

The Smart Grid (SG) implementation requires a constant monitoring and control of the power network. An Advanced Metering Infrastructure (AMI) allows the Distribution System Operator (DSO) to know what is happening on the power network. However, existing smart meters are not prepared for an emerging energy market nor to be integrated with LV/MV dispatch centres. The Unbundle Smart Meter (USM) concept allows the integration of existing smart meters in the SG, decreasing deployment costs. This paper presents the USM approach for power inverters management. The USM acts as a residential gateway, enabling the control of energy home devices using an IP-based secure communication network. The USM hosts the necessary services and drivers to provide the end-user with the capability to answer Demand Response (DR) requests from the DSO.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Towards PVT-Tolerant Glitch-Free Operation in FPGAs 16

Towards PVT-Tolerant Glitch-Free Operation in FPGAs

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Huda, Safeen Anderson, Jason Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781450338561

Glitches are unnecessary transitions on logic signals that needlessly consume dynamic power. Glitches arise from imbalances in the combinational path delays to a signal, which may cause the signal to toggle multiple times in a given clock cycle before settling to its final value. In this paper, we propose a low-cost circuit structure that is able to eliminate a majority of glitches. The structure, which is incorporated into the output buffers of FPGA logic elements, suppresses pulses on buffer outputs whose duration is shorter than a configurable time window (set at the time of FPGA configuration). Glitches are thereby eliminated "at the source" ensuring they do not propagate into the high-capacitance FPGA interconnect, saving power. An experimental study, using Altera commercial tools for power analysis, demonstrates that the proposed technique reduces 70% of glitches, at a cost of 1% reduction in speed performance.

关键词： field programmable gate arrays (FPGA)

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A High-SNR Normal Approximation for Single-Antenna Rayleigh Block-Fading Channels

A High-SNR Normal Approximation for Single-Antenna Rayleigh ...

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IEEE international symposium on Information Theory (ISIT)

作者： Lancho, Alejandro Koch, Tobias Durisi, Giuseppe Univ Carlos III Madrid Leganes Spain Gregorio Maranon Hlth Res Inst Madrid Spain Chalmers Univ Technol Gothenburg Sweden

ISBN: (纸本)9781509040964

This paper concerns the maximal achievable rate at which data can be transmitted over a non-coherent, single antenna, Rayleigh block-fading channel using an error-correcting code of a given blocklength with a block-error probability not exceeding a given value. In particular, a high-SNR normal approximation of the maximal achievable rate is presented that becomes accurate as the signal-to-noise ratio (SNR) and the number of coherence intervals L over which we code tend to infinity. Numerical analyses suggest that the approximation is accurate already at SNR values of 15 dB.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Maritime Moving Target Detection Technique for Passive Bistatic Radar with GNSS Transmitters 18

Maritime Moving Target Detection Technique for Passive Bista...

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18th international Radar symposium (IRS)

作者： Santi, Fabrizio Pastina, Debora Bucciarelli, Marta Sapienza Univ Rome Dept Informat Engn Elect & Telecommun Via Eudossiana 18 I-00184 Rome Italy Sympas Srl Viale Giulio Cesare 71 I-00192 Rome Italy

ISBN: (纸本)9783736993433

The paper puts forward a moving target detection technique for passive bistatic radar systems based on GNSS signals for maritime surveillance applications. If from one hand navigation satellites are extremely attractive as opportunistic sources for passive radar due to their global coverage and the availability of multiple satellites, on the other hand they provide a restricted power budget. To strengthen the target energy sufficiently to allow its detection, observation time has to be increased up to several tens of seconds. This requires the need to develop innovative techniques able to deal with such long integration times. In this paper, a local plane-based maritime moving target detection (MMTD) technique is proposed. Such a technique performs the integration of the received signal for a long integration time, properly taking into account the migration of the moving target during the entire dwell time. Moreover, it provides target detection in the local plane that represents the section of maritime area covered by the radar antenna. Since this plane is common to multiple transmitters, the proposed technique can be easily extended to the multistatic case, which is the bigger benefit in using GNSS sources. Simulated and experimental results confirm the effectiveness of the proposed M-MTD technique to detect ship targets, not detectable with conventional MTD techniques, with the GNSS-based passive radar.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL 2017

Acceleration of the aggregation process in a Hall-thruster s...

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8th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Noda, Hiroyuki Sakai, Ryotaro Miyajima, Takaaki Fujita, Naoyuki Amano, Hideharu Keio Univ 3-14-1 Hiyoshi Yokohama Kanagawa 2238522 Japan Japan Aerosp Explorat Agcy JAXA 7-44-1 Jindaiji Higashi Chofu Tokyo 1828522 Japan

ISBN: (纸本)9781450353168

The Full Particle-In-Cell (Full-PIC) method is a numerical simulation technique used in the research and development of Hall-thrusters which are a type of electric propulsion engines. It treats ions, neutrons, and electrons as particles and is highly accurate compared with other methods which treat them as a fluid. However, it requires a large computational cost. The Japan Aerospace Exploration Agency (JAXA) is developing a software package called NSRU-Full-PIC that implements such a method. One of the important computing tasks in NSRU-Full-PIC is the aggregation process, which causes Read-After-write (RAW) hazards, and hence makes parallel computation difficult. In this paper, we tackle this problem by introducing a reduction operation with an FPGA accelerator. We use Intel's mid-range SoC, Arria 10 which embeds floating-point DSPs for high performance numerical computation. Intel FPGA SDK for OpenCL is available for this platform for easy offloading of complex tasks. We implemented 4 types reduction kernels and compared their performance. As a result, the aggregation process becomes 76.4 times faster than the single-thread version on an ARM Cortex-A9 1.5 GHz, and 14.1 times faster than that on a Xeon E5-2660 2.9 GHz in our fastest implementation, Read-16-Vect. In this implementation, we achieved 93.5% of theoretical performance with optimized FPGA resources.

关键词： field programmable gate arrays (FPGA)

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Benefits of Cache Assignment on Degraded Broadcast Channels

Benefits of Cache Assignment on Degraded Broadcast Channels

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IEEE international symposium on Information Theory (ISIT)

作者： Bidokhti, Shirin Saeedi Wigger, Michele Yener, Aylin Stanford Univ Stanford CA 94305 USA Penn State Univ University Pk PA 16802 USA Univ Paris Saclay LTCI Telecom ParisTech F-75013 Paris France

ISBN: (纸本)9781509040964

The degraded K-receiver broadcast channel (BC) is studied when receivers are aided with cache memories. Lower and upper bounds are derived on the capacity-memory tradeoff, i.e., on the largest rate that can he achieved as a function of the receivers' cache sizes. The lower bounds are achieved by two new coding schemes that benefit from non-uniform cache assignment. The paper also provides lower and upper hounds on the global capacity-memory tradeoff of degraded BCs, i.e., on the largest capacity-memory tradeoff that can be attained by optimizing the receivers cache-assignment subject to a total cache memory budget. The bounds coincide when the total cache memory budget is sufficiently small or sufficiently large, with the thresholds depending on the BC statistics. For a small total cache budget M, it is optimal to assign all the cache memory to the weakest receiver. In this regime, the global capacity-memory tradeoff grows as M/D, where D denotes the total number of files in the system. For a large total cache budget, it is optimal to assign a positive cache memory to every receiver, where weaker receivers are assigned larger cache memories than stronger receivers. When the total cache budget M exceeds a threshold, then the global capacity-memory tradeoff grows as 1/K . M/D. A uniform cache-assignment policy is suboptimal.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths 16

GPU-Accelerated High-Level Synthesis for Bitwidth Optimizati...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Kapre, Nachiket Ye, Deheng Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

ISBN: (纸本)9781450338561

Bitwidth optimization of FPGA datapaths can save hardware resources by choosing the fewest number of bits required for each datapath variable to achieve a desired quality of result. However, it is an NP-hard problem that requires unacceptably long runtimes when using sequential CPU-based heuristics. We show how to parallelize the key steps of bitwidth optimization on the GPU by performing a fast brute-force search over a carefully constrained search space. We develop a high-level synthesis methodology suitable for rapid prototyping of bitwidth-annotated RTL code generation using gcc's GIMPLE backend. For range analysis, we perform parallel evaluation of sub-intervals to provide tighter bounds compared to ordinary interval arithmetic. For bitwidth allocation, we enumerate the different bitwidth combinations in parallel by assigning each combination to a GPU thread. We demonstrate up to 10-1000x speedups for range analysis and 50-200x speedups for bitwidth allocation when comparing NVIDIA K20 GPU implementation to an Intel Core i5-4570 CPU while maintaining identical solution quality across various benchmarks. This allows us to generate tailor-made RTL with minimum bitwidths in hundreds of milliseconds instead of hundreds of minutes when starting from high-level C descriptions of dataflow computations.

关键词： field programmable gate arrays (FPGA)

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FCUDA-SoC: Platform Integration for field-programmable SoC with the CUDA-to-FPGA Compiler 16

FCUDA-SoC: Platform Integration for Field-Programmable SoC w...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Nguyen, Tan Gurumani, Swathi Rupnow, Kyle Chen, Deming Adv Digital Sci Ctr Singapore Singapore Univ Illinois Elect & Comp Engn Urbana IL 61801 USA

ISBN: (纸本)9781450338561

Throughput oriented high level synthesis allows efficient design and optimization using parallel input languages. Parallel languages offer the benefit of parallelism extraction at multiple levels of granularity, offering effective design space exploration to select efficient single core implementations, and easy scaling of parallelism through multiple core instantiations. However, study of high level synthesis for parallel languages has concentrated on optimization of core and on-chip communications, while neglecting platform integration, which can have a significant impact on achieved performance. In this paper, we create an automated flow to perform efficient platform integration for an existing CUDAto-RTL throughput oriented HLS, and we open source the FCUDA tool, platform integration, and benchmark applications. We demonstrate platform integration of 16 benchmarks on two Zynq-based systems in bare-metal and OS mode. We study implementation optimization for platform integration, compare to an embedded GPU (Tegra TK1) and verify designs on a Zedboard Zynq 7020 (bare-metal) and Omnitek Zynq 7045 (OS).

关键词： System-on-chip

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Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper 16

Dissecting Xeon + FPGA: Why the integration of CPUs and FPGA...

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21st IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2016

作者： Schmit, Herman Huang, Randy Intel Corporation San JoseCA United States

ISBN: (纸本)9781450341851

Intel's Xeon roadmap includes package-integrated FPGAs in every new generation. In this talk, we will dissect why this is such a powerful combination at this time of great change in datacenter workloads. We will show how power savings within the CPU complex is a significant multiplier for power savings in the datacenter as a whole. Focusing on the domain of machine learning, we will present the recent evolution of data types and operators, and make the case that FPGAs are the path to facilitate this continued evolution. Finally, we will discuss the criticality of the close coupling of the CPU and the FPGA. This coupling facilitates high bandwidth and low latency communication that is required for the development, debugging and deployment of heterogeneous applications. © 2016 Authors.

关键词： field programmable gate arrays (FPGA)

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On the Automation of High Level Synthesis of Convolutional Neural Networks 30

On the Automation of High Level Synthesis of Convolutional N...

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30th IEEE international Parallel and Distributed Processing symposium (IPDPS)

作者： Del Sozzo, Emanuele Solazzo, Andrea Miele, Antonio Santambrogio, Marco D. Politecn Milan Dipartimento Elett Informaz & Bioingn Milan Italy

ISBN: (纸本)9781509036820

Convolutional Neural Networks (CNNs) are a particular type of Artificial Neural Networks (ANNs) inspired by cells in the primary visual cortex of animals, and represent the state of the art in image recognition and classification. Nowadays, such supervised learning technique is very popular in Big Data analytics. In this context, due to the huge amount of data to be processed, it is crucial to find techniques to speed up the computation. In particular, the dataflow pattern of CNN algorithm results to be suitable for hardware acceleration. This paper proposes a framework to automatically generate a hardware implementation of CNNs on field programmable gate arrays (FPGAs), based on the High Level Synthesis (HLS) of configurable offline-trained networks.

关键词： field programmable gate arrays Convolutional Neural Networks High Level Synthesis

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