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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 834 条记录，以下是231-240 订阅

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Keynote: A new Silicon Age 4.0: Generating semiconductor-intelligence paradigm with a Virtual Moore's Law Economics and Heterogeneous technologies

Keynote: A new Silicon Age 4.0: Generating semiconductor-int...

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international symposium on Low Power Electronics and Design (ISLPED)

作者： Nicky Liu Etron Technology Inc. Hsinchu Taiwan

ISBN: (纸本)9781509060245

The future of the silicon-based economy will not be as pessimistic as some commentators have argued, given their predictions of the end of Moore's Law Economy (ME) by the early 2020s. On the contrary, a Virtual Moore's Law Economy (VME) will develop and thrive, advancing innovation by a new Silicon Way of producing various application-driven Heterogeneous Integrated (HI) Nano-systems by optimization of physics, materials, devices, circuits/chips, software and systems to enable exciting applications for business growth. The semiconductor industry will enjoy sufficient financial returns from new application and system-product sales, even considering more expensive silicon investment. Such a technological approach based on a (Function × Value)-Scaling Down-Plus-Up Methodology, in addition to Linear-Scaling, Area-Scaling and Volumetric-Scaling Methodologies, can fundamentally change the way of thinking and execution toward optimizing coherently both technology definition and final system design with an holistic HIDAS (HI Design/Architecture/System) method. This will drive IC scaling to an effective 1-Nanometer Realm, stimulating a thriving silicon industry which can have at least 30 more years of growth toward a 1 trillion-dollar size.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Inter-FPGA Routing Environment for Performance Exploration of Multi-FPGA Systems 27

Inter-FPGA Routing Environment for Performance Exploration o...

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27th international symposium on Rapid System Prototyping (RSP) - Shortening the Path from Specification to Prototype

作者： Farooq, Umer Chotin-Avot, Roselyne Azeem, Moazam Ravoson, Maminionja Turki, Mariem Mehrez, Habib UPMC Univ Paris 06 Sorbonne Univ CNRS LIP6 Paris France

ISBN: (纸本)9781450345354

Multi-FPGA platforms are a popular choice today for complex system prototyping because they offer high execution speed, low cost, and real world testing experience. However, performance of multi-FPGA based systems is severely affected by widening logic to I/O gap in FPGAs. In order to address the performance issue, in this work, we propose an exploration and optimization flow for multi-FPGA based prototyping that gives an end-to-end experience starting from benchmark generation to optimized inter-FPGA routing. Using generic tools of the flow, ten large benchmarks are generated. Then, through a generic novel inter-FPGA routing environment, effect of variation of number of FPGAs as well as number of inter-FPGA tracks on the performance of a target design is explored. For performance exploration and optimization, five different FPGA boards are utilized where number of FPGAs on board are varied from two to six. Moreover, for each board four different inter-FPGA track combinations are used. Experimental results reveal that multi-FPGA boards with inter-FPGA tracks corresponding optimally to the cut net requirements of benchmarks under consideration give best frequency results. Furthermore, frequency comparison between different boards shows that FPGA board with six FPGAs gives, on average, best frequency results. Finally, we also perform frequency-price analysis which shows that board with four FPGAs gives better frequency-price tradeoff as compared to other FPGA boards under consideration.

关键词： field programmable gate arrays Routing Benchmark testing Computer architecture Program processors Target tracking Optimization

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FPGA 2013 - proceedings of the 2013 acm/sigda international symposium on field programmable gate arrays

FPGA 2013 - Proceedings of the 2013 ACM/SIGDA International ...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

ISBN: (纸本)9781450318877

The proceedings contain 29 papers. The topics discussed include: accelerating subsequence similarity search based on dynamic time warping distance with FPGA;video-rate stereo matching using Markov random field TRW-S inference on a hybrid CPU+FPGA computing platform;fully-functional FPGA prototype with fine-grain programmable body biasing;sensing nanosecond-scale voltage attacks and natural transients in FPGAs;word-length optimization beyond straight line code;word-length optimization beyond straight line code;embedding-based placement of processing element networks on FPGAs for physical model simulation;a remote memory access infrastructure for global address space programming models in FPGAs;architecture support for custom instructions with memory operations;high throughput and programmable online traffic classifier on FPGA;and indirect connection aware attraction for FPGA clustering.

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Bypassing parity protected cryptography using laser fault injection in cyber-physical system 2

Bypassing parity protected cryptography using laser fault in...

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2nd acm international Workshop on Cyber-Physical System Security, CPSS 2016

作者： He, Wei Breier, Jakub Bhasin, Shivam Chattopadhyay, Anupam PACE Temasek Labortaries Nanyang Technological University Singapore Singapore School of Computer Engineering Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781450342889

Lightweight cryptography has been widely utilized in resource constrained embedded devices of Cyber-Physical System (CPS) terminals. The hostile and unattended environment in many scenarios make those endpoints easy to be attacked by hardware based techniques. As a resource-efficient countermeasure against Fault Attacks, parity Concurrent Error Detection (CED) is preferably integrated with security-critical algorithm in CPS terminals. The parity bit changes if an odd number of faults occur during the cipher execution. In this paper, we analyze the effectiveness of fault detection of a parity CED protected cipher (PRESENT) using laser fault injection. The experimental results show that the laser perturbation to encryption can easily flip an even number of data bits, where the faults cannot be detected by parity. Due to the similarity of different parity structures, our attack can bypass almost all parity protections in block ciphers. Some suggestions are given to enhance the security of parity implementations. © 2016 acm.

关键词： field programmable gate arrays (FPGA)

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On How to Improve FPGA-Based Systems Design Productivity via SDAccel 30

On How to Improve FPGA-Based Systems Design Productivity via...

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30th IEEE international Parallel and Distributed Processing symposium (IPDPS)

作者： Guidi, Giulia Reggiani, Enrico Di Tucci, Lorenzo Durelli, Gianluca Blott, Michaela Santambrogio, Marco D. Politecn Milan Dipartimento Elett Informaz & Bioingn Milan Italy

ISBN: (纸本)9781509036820

Custom hardware accelerators are widely used to improve the performance of software applications in terms of execution times and to reduce energy consumption. However the realization of an hardware accelerator and its integration in the final system is a difficult and error prone task. For this reason, both Industry and Academy are continuously developing Computer Aided Design (CAD) tools to assist the designer in the development process. Even if many of the steps have been nowadays automated, system integration and SW/HW interfaces definition and drivers generation are still almost completely manual tasks. The last tool released by Xilinx, however, aims at improving the hardware design experience by leveraging the OpenCL standard to enhance the overall productivity and to enable code portability. This paper provides an overview of the SDAccel potentiality comparing its design flow with other methodologies using two case studies from the Bioinformatics field: brain network and protein folding analysis.

关键词： field programmable gate arrays (FPGA)

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Extending the Moore's law by exploring new data center architecture: Invited Paper 16

Extending the Moore's law by exploring new data center archi...

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21st IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2016

作者： Ouyang, Jian Qi, Wei Wang, Yong Baidu Baidu Campus Beijing China

ISBN: (纸本)9781450341851

In recent ten years, lots of new applications emerged, such as AI, big data and cloud. Though the workloads of these applications are very diverse, they demand huge resource of data center. In contrast, the silicon technology moves slower and slower because the Moore's law is going to the end. Consequently, the data center building from commodity hardware cannot provide enough costefficiency and power-efficiency. To meet the increasingly resource needs of emerging applications, the scale of data center is become much larger and larger. It consumes huge power and cost of hardware. From the business perspective, the slow development of hardware technology limits the value creation of emerging applications. We, Baidu, the largest search engine in China, have faced this challenge in several years ago. We find that the server number increases much faster than the scale of business. And this case is common for internet companies. Because the iteration of general processor becomes slower and slower. For example, Intel announced that the Tick-Tock production strategic was out of date in this early year. This problem drive us to look for new methods to boost business. From Internet Company's perspective, building new chips or new architecture based on its applications' characteristics makes sense. This method can break the limitation of commodity chips and commodity hardware. And according to academic and industry experiences, domain-specified architecture can achieve much better performance and power efficiency than general architecture. Consequently, we are exploring new architecture to extend Moore's law. In this paper, we present the works on exploring new architecture for data center. The data center resource includes storage, memory, computing and networking. Hence, we focus on these four areas. Firstly, we implemented SDF for large-scale distributed storage system. The SDF aims to low cost and high performance flash storage system. Secondly, we implemented SDA for dee

关键词： field programmable gate arrays (FPGA)

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Automatic Generation of Efficient Accelerators for Reconfigurable Hardware 16

Automatic Generation of Efficient Accelerators for Reconfigu...

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43rd acm/IEEE Annual international symposium on Computer Architecture (ISCA)

作者： Koeplinger, David Prabhakar, Raghu Zhang, Yaqi Delimitrou, Christina Kozyrakis, Christos Olukotun, Kunle Stanford Univ Stanford CA 94305 USA Cornell Univ Ithaca NY 14853 USA Ecole Polytech Fed Lausanne Lausanne Switzerland

ISBN: (纸本)9781467389471

Acceleration in the form of customized datapaths offer large performance and energy improvements over general purpose processors. Reconfigurable fabrics such as FPGAs are gaining popularity for use in implementing application-specific accelerators, thereby increasing the importance of having good high-level FPGA design tools. However, current tools for targeting FPGAs offer inadequate support for high-level programming, resource estimation, and rapid and automatic design space exploration. We describe a design framework that addresses these challenges. We introduce a new representation of hardware using parameterized templates that captures locality and parallelism information at multiple levels of nesting. This representation is designed to be automatically generated from high-level languages based on parallel patterns. We describe a hybrid area estimation technique which uses template-level models and design-level artificial neural networks to account for effects from hardware place-and-route tools, including routing overheads, register and block RAM duplication, and LUT packing. Our runtime estimation accounts for off-chip memory accesses. We use our estimation capabilities to rapidly explore a large space of designs across tile sizes, parallelization factors, and optional coarse-grained pipelining, all at multiple loop levels. We show that estimates average 4.8% error for logic resources, 6.1% error for runtimes, and are 279 to 6533 times faster than a commercial high-level synthesis tool. We compare the best-performing designs to optimized CPU code running on a server-grade 6 core processor and show speedups of up to 16.7x.

关键词： field programmable gate arrays Hardware Pipeline processing Space exploration Estimation Design tools

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Design Guidelines for Embeded NoCs on FPGAs 17

Design Guidelines for Embeded NoCs on FPGAs

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17th international symposium on Quality Electronic Design (ISQED)

作者： Gamal, Noha Fahmy, Hossam Ismail, Yehea Mostafa, Hassan Mentor Graph Corp Wilsonville OR 97070 USA Cairo Univ Elect & Commun Engn Dept Giza 12613 Egypt Zewail City Sci & Technol CND Giza Egypt AUC New Cairo 11835 Egypt

ISBN: (纸本)9781509012138

Including Networks-on-Chip (NoCs) within FPGAs has become necessary to overcome the problems of point-to-point interconnect scheme. This will enable interfacing with high speed IOs and partial dynamic reconfiguration (PDR), reduce the compile time and improve the system performance. We compared FPGA-specific NoC components on soft and hard implementations and analyzed the efficiency gap between the two technologies to get design constraints in this space. Input module that includes memory buffers, implemented using block RAMs (BRAMs), is the module with the smallest gaps: 1.8x area, 2.9x delay and 53x power. Switch has the largest gap: 90x area, 7x delay and 53x power. If the router is totally hard implemented, this will save 9x area, 3.7x delay and 12x power at the expense of no flexibility (reconfigurability). By comparing our results with same flow on ASIC-specific router, we show that using FPGA-specific NoCs design improves the utility by a factor of 3x in area with a slight increase in the delay.

关键词： field programmable gate arrays (FPGA)

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acm/sigda international symposium on field programmable gate arrays - FPGA: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 2013年 iii页

作者： Hutchings, Brad Betz, Vaughn Brigham Young University United States University of Toronto Canada

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RapidSmith 2: A framework for BEL-level CAD exploration on Xilinx FPGAs 15

RapidSmith 2: A framework for BEL-level CAD exploration on X...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Haroldsen, Travis Nelson, Brent Hutchings, Brad Department of Electrical and Computer Engineering Brigham Young University ProvoUT84602 United States

ISBN: (纸本)9781450333153

RapidSmith is an open-source framework that allows for the exploration of novel approaches to the FPGA CAD flow for Xilinx devices. However, RapidSmith has poor sup- port for manipulating designs below the slice level. In this paper, we highlight many of the projects RapidSmith en- ables and present extensions incorporated into "RapidSmith 2" that expose LUTs and ip-ops for direct manipulation in custom-built CAD tools. To demonstrate the utility of RapidSmith 2 we present the results of work to identify BELs in a design which must be clustered together and a tool that does pre-packing clustering accordingly. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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