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From high-level deep neural models to FPGAS 49

From high-level deep neural models to FPGAS

引用

49th Annual IEEE/acm international symposium on Microarchitecture, MICRO 2016

作者： Sharma, Hardik Park, Jongse Mahajan, Divya Amaro, Emmanuel Kim, Joon Kyung Shao, Chenkai Mishra, Asit Esmaeilzadeh, Hadi Lab School of Computer Science Georgia Institute of Technology United States Intel Corporation United States

ISBN: (纸本)9781509035083

Deep Neural Networks (DNNs) are compute-intensive learning models with growing applicability in a wide range of domains. FPGAS are an attractive choice for DNNs since they offer a programmable substrate for acceleration and are becoming available across different market segments. However, obtaining both performance and energy efficiency with FPGAS is a laborious task even for expert hardware designers. Furthermore, the large memory footprint of DNNs, coupled with the FPGAS' limited on-chip storage makes DNN acceleration using FPGAS more challenging. This work tackles these challenges by devising DnnWeaver, a framework that automatically generates a synthesizable accelerator for a given (DNN, FPGA) pair from a high-level specification in Caffe [1]. To achieve large benefits while preserving automation, DNNWEAVER generates accelerators using hand-optimized design templates. First, DnnWeaver translates a given high-level DNN specification to its novel ISA that represents a macro dataflow graph of the DNN. The DnnWeaver compiler is equipped with our optimization algorithm that tiles, schedules, and batches DNN operations to maximize data reuse and best utilize target FPGA's memory and other resources. The final result is a custom synthesizable accelerator that best matches the needs of the DNN while providing high performance and efficiency gains for the target FPGA. We use DnnWeaver to generate accelerators for a set of eight different DNN models and three different FPGAS, Xilinx Zynq, Altera Stratix V, and Altera Arria 10. We use hardware measurements to compare the generated accelerators to both multicore CPUs (ARM Cortex A15 and Xeon E3) and many-core GPUs (Tegra K1, GTX 650Ti, and Tesla K40). In comparison, the generated accelerators deliver superior performance and efficiency without requiring the programmers to participate in the arduous task of hardware design. © 2016 IEEE.

关键词： field programmable gate arrays (FPGA)

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Design space exploration of L1 data caches for FPGA-based multiprocessor systems 15

Design space exploration of L1 data caches for FPGA-based mu...

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Matthews, Eric Doyle, Nicholas C. Shannon, Lesley Simon Fraser University 8888 University Drive BurnabyBCV5A 1S6 Canada

ISBN: (纸本)9781450333153

Combining multi-processing with the high level of configurability possible with FPGA-based soft-processors, this paper presents a multiprocessing framework based on the MicroBlaze soft-processor that provides multicore support and fully coherent, independently configurable Level 1 Caches with Linux multicore support. This architecture allows for finegrain configurability of the system, allowing for FPGA resources to be better optimized for a specific embedded application. We use our framework to explore the L1 Data Cache configuration, developing a metric for efficiency based on resource usage and static application runtime. We find that a Pseudo-Random replacement policy is consistently the more efficient choice for FPGA systems.

关键词： field programmable gate arrays (FPGA)

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0.5-V highly power-efficient programmable logic using nonvolatile configuration switch in BEOL 15

0.5-V highly power-efficient programmable logic using nonvol...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Miyamura, Makoto Sakamoto, Toshitsugu Tsuji, Yukihide Tada, Munehiro Banno, Naoki Okamoto, Koichiro Iguchi, Noriyuki Hada, Hiromitsu West 7 16-1 Onogawa Tsukuba Ibaraki305-8569 Japan

ISBN: (纸本)9781450333153

A low-power nonvolatile programmable-logic cell array is proposed for energy-constrained applications such as wireless sensor nodes and mobile apparatuses. A 64 ×64 programmablelogic cell array includes a 9.2-Mbit nonvolatile switch, namely atom switch, as the routing switch and configuration memory. A 16-bit arithmetic logic unit, which is a building block of the micro-controller unit, was implemented to compare the speed and power consumption with a state-of-the-art low power fieldprogrammable gate array. The proposed programmable-logic array exhibited 30% dynamic power saving and x2.5 faster operation in the low-voltage region. Zero sleep power was also demonstrated.

关键词： Sensor nodes

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High-level design tools for floating point FPGAs 15

High-level design tools for floating point FPGAs

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Singh, Deshanand P. Pasca, Bogdan Czajkowski, Tomasz S. Altera Corporation 150 Bloor Street West TorontoON Canada Altera Corporation Westwood High Wycombe BuckinghamshireHP12 4PU United Kingdom

ISBN: (纸本)9781450333153

This tutorial describes tools for efficiently implementing floating point applications on FPGAs. We present both the SDK for OpenCL and DSP Builder Advanced Blockset and show that they can be effectively used to implement many floating point applications. The methods for optimizing application performance are also described. In this tutorial we focus on a few applications, including Fast Fourier transform, matrix multiplication, finite impulse response filter and a Cholesky decomposition. In all cases we show what the tools are capable of achieving, and more importantly how a user can take advantage of the various floating-point centric features that are made available. We also discuss how these tools can automatically use FPGA architectural features such as hardened floating-point DSP available on Altera Arria 10 family. © Copyright 2015 acm.

关键词： field programmable gate arrays (FPGA)

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Stochastic-Based Spin-programmable gate Array with Emerging MTJ Device Technology (Abstract Only) 16

Stochastic-Based Spin-Programmable Gate Array with Emerging ...

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proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Yu Bai Mingjie Lin University of Central Florida Orlando FL USA

ISBN: (纸本)9781450338561

This paper describes the stochastic-based Spin-programmable gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in FPGAs, our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure. Our mixed mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10x improvement in logic density, about 5x improvement in average net delay, and about 5x improvement in the critical path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits.

关键词： stochastic fpga emerging devices

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Technology mapping into general programmable cells 15

Technology mapping into general programmable cells

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Mishchenko, Alan Brayton, Robert Feng, Wenyi Greene, Jonathan Department of EECS University of California Berkeley United States Microsemi Corporation SOC Products Group United States

ISBN: (纸本)9781450333153

field-programmable gate arrays (FPGA) implement logic functions using programmable cells, such as K-input lookuptables (K-LUTs). A K-LUT can implement any Boolean function with K inputs and one output. Methods for mapping into K-LUTs are extensively researched and widely used. Recently, cells other than K-LUTs have been explored, for example, those composed of several LUTs and those combining LUTs with several gates. Known methods for mapping into these cells are specialized and complicated, requiring a substantial effort to evaluate custom cell architectures. This paper presents a general approach to efficiently map into single-output K-input cells containing LUTs, MUXes, and other elementary gates. Cells with to 16 inputs can be handled. The mapper is fully automated and takes a logic network and a symbolic description of a programmable cell, and produces an optimized network composed of instances of the given cell. Past work on delay/area optimization during mapping is applicable and leads to good quality of results.

关键词： Boolean functions

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Floating-point DSP block architecture for FPGAs 15

Floating-point DSP block architecture for FPGAs

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Langhammer, Martin Pasca, Bogdan Altera European Technology Centre United Kingdom

ISBN: (纸本)9781450333153

This work describes the architecture of a new FPGA DSP block supporting both fixed and floating point arithmetic. Each DSP block can be configured to provide one single precision IEEE-754 floating multiplier and one IEEE-754 floating point adder, or when configured in fixed point mode, the block is completely backwards compatible with current FPGA DSP blocks. The DSP block operating frequency is similar in both modes, in the region of 500MHz, offering up to 2 GMACs fixed point and 1 GFLOPs performance per block. In floating point mode, support for multi-block vector modes are provided, where multiple blocks can be seamlessly assembled into any size real or complex dot products. By efficient reuse of the fixed point arithmetic modules, as well as the fixed point routing, the floating point features have only minimal power and area impact. We show how these blocks are implemented in a modern Arria 10 FPGA family, offering over 1 TFLOPs using only embedded structures, and how scaling to multiple TFLOPs densities is possible for planned devices. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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On data forwarding in deeply pipelined soft processors 15

On data forwarding in deeply pipelined soft processors

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Cheah, Hui Yan Fahmy, Suhaib A. Kapre, Nachiket School of Computer Engineering Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781450333153

We can design high-frequency soft-processors on FPGAs that exploit deep pipelining of DSP primitives, supported by selective data forwarding, to deliver up to 25% performance improvements across a range of benchmarks. Pipelined, inorder, scalar processors can be small and lightweight but suffer from a large number of idle cycles due to dependency chains in the instruction sequence. Data forwarding allows us to more deeply pipeline the processor stages while avoiding an associated increase in the NOP cycles between dependent instructions. Full forwarding can be prohibitively complex for a lean soft processor, so we explore two approaches: an external forwarding path around the DSP block execution unit in FPGA logic and using the intrinsic loopback path within the DSP block primitive. We show that internal loopback improves performance by 5% compared to external forwarding, and up to 25% over no data forwarding. The result is a processor that runs at a frequency close to the fabric limit of 500MHz, but without the significant dependency overheads typical of such processors. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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Superoptimized memory subsystems for streaming applications 15

Superoptimized memory subsystems for streaming applications

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Wingbermuehle, Joseph G. Cytron, Ron K. Chamberlain, Roger D. Dept. of Computer Science and Engineering Washington University in St. Louis United States

ISBN: (纸本)9781450333153

Because main memory is many times slower than modern processor cores, deep, multi-level cache hierarchies are ubiquitous in computers today. Similarly, applications deployed on ASICs and FPGAs are often hindered by slow external memories. Therefore, to achieve good performance, hardware designers must optimize main memory usage. Unfortunately, this process is often labor intensive and fails to explore the full range of potential memory designs. To address this issue for applications expressed in a streaming manner, we show that it is possible to generate automatically a superoptimized memory subsystem that can be deployed on an FPGA such that it performs better than a general-purpose memory subsystem. Rather than explore only simple memory subsystems, our superoptimizer is capable of exploring extremely complex designs consisting of multi-level caches and other components. Finally, we show that it is possible to deploy applications with superoptimized memory subsystems with minimal additional effort while achieving significant performance improvements over a naive memory subsystem.

关键词： field programmable gate arrays (FPGA)

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Enhancements in UltraScale CLB architecture 15

Enhancements in UltraScale CLB architecture

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Chandrakar, Shant Gaitonde, Dinesh Bauer, Trevor Xilinx Inc. Hyderabad India Xilinx Inc. San JoseCA United States Xilinx Inc. LongmontCO United States

ISBN: (纸本)9781450333153

Each generation of FPGA architecture benefits from optimizations around its technology node and target usage. In this paper, we discuss some of the changes made to the CLB for Xilinx's 20nm UltraScale product family. We motivate those changes and demonstrate better results than previous CLB architectures on a variety of metrics. We show that, in demanding scenarios, logic placed in an UltraScale device requires 16% less wirelength than 7-series. Designs mapped to UltraScale devices also require fewer logic tiles. In this paper, we demonstrate the utilization benefits of the Ultra-Scale CLB attributed to certain CLB enhancements. The enhancements described herein result in an average packing improvement of 3% for the example design suite. We also show that the UltraScale architecture handles aggressive, tighter packing more gracefully than previous generations of FPGA. These significant reductions in wirelength and CLB counts translate directly into power, performance and ease-of-use benefits.

关键词： field programmable gate arrays (FPGA)

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