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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Fine-grained interconnect synthesis 15

Fine-grained interconnect synthesis

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Rodionov, Alex Biancolin, David Rose, Jonathan Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Canada

ISBN: (纸本)9781450333153

One of the key challenges for the FPGA industry going forward is to make the task of designing hardware easier. A significant portion of that design task is the creation of the interconnect pathways between functional structures. We present a synthesis tool that automates this process and focuses on the interconnect needs in the fine-grained (sub-IP-block) design space. Here there are several issues that prior research and tools do not address well: the need to have fixed, deterministic latency between communicating units (to enable high-performance local communication without the area overheads of latency-insensitivity), and the ability to avoid generating un-necessary arbitration hardware when the application design can avoid it. Using a design example, our tool generates interconnect that requires 72% fewer lines of specification code than a hand-written Verilog implementation, which is a 33% overall reduction for the entire application. The resulting system, while requiring 4% more total functional and interconnect area, achieves the same performance. We also show a quantitative and qualitative advantages against an existing commercial interconnect synthesis tool, over which we achieve a 25% performance advantage and 17%/57% logic/memory area savings.

关键词： field programmable gate arrays (FPGA)

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InTime: A machine learning approach for efficient selection of FPGA CAD tool parameters 15

InTime: A machine learning approach for efficient selection ...

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Kapre, Nachiket Ng, Harnhua Teo, Kirvy Naude, Jaco Nanyang Technological University Singapore Singapore Plunify Inc. Singapore Singapore

ISBN: (纸本)9781450333153

FPGA CAD tool parameters controlling synthesis optimizations, place and route effort, mapping criteria along with user-supplied physical constraints can affect timing results of the circuit by as much as 70% without any change in original source code. A correct selection of these parameters across a diverse set of benchmarks with varying characteristics and design goals is challenging. The sheer number of parameters and option values that can be selected is large (thousands of combinations for modern CAD tools) with often conflicting interactions. In this paper, we present InTime, a machinelearning approach supported by a cloud-based (or clusterbased) compilation infrastructure for automating the selection of these parameters effectively to minimize timing costs. InTime builds a database of results from a series of preliminary runs based on canned configurations of CAD options. It then learns from these runs to predict the next series of CAD tool options to improve timing results. Towards the end, we rely on a limited degree of statistical sampling of certain options like placer and synthesis seeds to further tighten results. Using our approach, we show 70% reduction in final timing results across industrial benchmark problems for the Altera CAD flow. This is 30% better than vendor-supplied design space exploration tools that attempts a similar optimization using canned heuristics. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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Mapping-aware constrained scheduling for LUT-based FPGAs 15

Mapping-aware constrained scheduling for LUT-based FPGAs

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Tan, Mingxing Dai, Steve Gupta, Udit Zhang, Zhiru School of Electrical and Computer Engineering Cornell University IthacaNY United States

ISBN: (纸本)9781450333153

Scheduling plays a central role in high-level synthesis, as it inserts clock boundaries into the untimed behavioral model and greatly impacts the performance, power, and area of the synthesized circuits. While current scheduling techniques can make use of pre-characterized delay values of individual operations, it is difficult to obtain accurate timing estimation on a cluster of operations without considering technology mapping. This limitation is particularly pronounced for FPGAs where a large logic network can be mapped to only a few levels of look-up tables (LUT). In this paper, we propose MAPS, a mapping-aware constrained scheduling algorithm for LUT-based FPGAs. Instead of simply summing up the estimated delay values of individual operations, MAPS jointly performs technology mapping and scheduling, creating the opportunity for more aggressive operation chaining to minimize latency and reduce area. We show that MAPS can produce a latency-optimal solution, while supporting a variety of design timing requirements expressed in a system of difference constraints. We also present an efficient incremental scheduling technique for MAPS to effectively handle resource constraints. Experimental results with real-life benchmarks demonstrate that our proposed algorithm achieves very promising improvements in performance and resource usage when compared to a state-of-the-art commercial high-level synthesis tool targeting Xilinx FPGAs. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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Application of specific delay window routing for timing optimization in FPGA designs 15

Application of specific delay window routing for timing opti...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Wegley, Evan Zhang, Qinhai Lattice Semiconductor Corporation 2115 O'Nel Drive San JoseCA95131 United States

ISBN: (纸本)9781450333153

In addition to optimizing for timing performance and routability, commercial FPGA routing engines must also support various timing constraints enabling the designer to fine tune aspects of their design. The many intricacies of commercial FPGA architectures add difficulty to the problem of supporting such constraints. In this paper, we show how the method of specific delay window routing can be applied to optimize for these various timing constraints constituting both long-and short-path requirements. Additionally, we enhance existing methods of routing according to specified delay by using dual wave expansion instead of single wave expansion with target delay estimation in order to improve accuracy and support sparser, more varied interconnect structures. Our results show that specific delay window routing is well-suited for optimization targeting a variety of timing constraints, and that using dual wave expansion to eliminate the estimation part of the router's delay cost function enables the router to support tighter timing constraints. For a suite of designs with known hold timing violations, we found that the dual wave approach can correct all such violations, whereas the single wave approach failed to correct the hold timing violations for several designs. Furthermore, for a suite of designs with maximum skew constraints of 250 ps on certain nets and buses, the dual wave approach met the constraints for all designs, whereas the single wave approach failed to meet the constraints for a majority of the designs. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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Delay-bounded routing for shadow registers 15

Delay-bounded routing for shadow registers

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Hung, Eddie Levine, Joshua M. Stott, Edward Constantinides, George A. Luk, Wayne Department of Electrical and Electronic Engineering Imperial College London United Kingdom Department of Computing Imperial College London United Kingdom

ISBN: (纸本)9781450333153

The on-chip timing behaviour of synchronous circuits can be quantified at run-time by adding shadow registers, which allow designers to sample the most critical paths of a circuit at a different point in time than the user register would normally. In order to sample these paths precisely, the path skew between the user and the shadow register must be tightly controlled and consistent across all paths that are shadowed. Unlike a custom IC, FPGAs contain prefabricated resources from which composing an arbitrary routing delay is not trivial. This paper presents a method for inserting shadow registers with a minimum skew bound, whilst also reducing the maximum skew. To preserve circuit timing, we apply this to FPGA circuits post place-and-route, using only the spare resources left behind. We find that our techniques can achieve an average STA reported delay bound of ±200ps on a Xilinx device despite incomplete timing information, and achieve

关键词： field programmable gate arrays (FPGA)

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Energy-efficient discrete signal processing with field programmable analog arrays (FPAAs) 15

Energy-efficient discrete signal processing with field progr...

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Bai, Yu Lin, Mingjie Department of Electrical Engineering and Computer Science University of Central Florida OrlandoFL32765 United States

ISBN: (纸本)9781450333153

Large-scale field programmable analog array (FPAA) devices have made analog and analog-digital signal processing techniques accessible to a much wider community. However, largely due to its severe resource constraints, high noise sensitivity, and enormous design space, reconfigurable analog computing remains a niche in the DSP application space. In this paper, we develop a probabilistic-based methodology for designing and implementing the analog computing engines that specifically target at energy-efficient signal processing systems. We will first demonstrate how to decompose a given DSP application into various functional modules within the framework of probabilistic-based processing. Furthermore, we will show how these individual functional modules can be easily mapped to the limited selection of analog blocks found in an commercially available FPAA device: the PSoC chip platform from Cypress. To keep our study concrete, our implementation example focuses on the 1-D convolution module, a fundamental algorithmic building block in many applications of computer vision and artificial intelligence. In the end, we construct a complete image processing system based on the PSoC chip platform, and use the application of image key point extraction to demonstrate that our proposed approach to reconfigurable analog computing has considerable advantages in hardware usage, energy efficiency, and computing robustness over the traditional DSP approaches. © Copyright acm.

关键词： Digital signal processing

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Energy and memory efficient mapping of bitonic sorting on FPGA 15

Energy and memory efficient mapping of bitonic sorting on FP...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Chen, Ren Siriyal, Sruja Prasanna, Viktor Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles90089 United States

ISBN: (纸本)9781450333153

Parallel sorting networks are widely employed in hardware implementations for sorting due to their high data paral- lelism and low control overhead. In this paper, we propose an energy and memory efficient mapping methodology for implementing bitonic sorting network on FPGA. Using this methodology, the proposed sorting architecture can be built for a given data parallelism while supporting continuous data streams. We propose a streaming permutation network (SPN) by "folding" the classic Clos network. We prove that the SPN is programmable to realize all the interconnection patterns in the bitonic sorting network. A low cost design for sorting with minimal resource usage is obtained by reusing one SPN. We also demonstrate a high throughput design by trading off area for performance. With a data parallelism of p (2≤ p≤ N= log2 N), the high throughput design sorts an N-key sequence with latency O(N=p), throughput (# of keys sorted per cycle) O(p) and uses O(N) memory. This achieves optimal memory efficiency (defined as the ratio of throughput to the amount of on-chip memory used by the design) of O(p=N). Another noteworthy feature of the high throughput design is that only single-port memory rather than dual-port memory is required for processing continu- ous data streams. This results in 50% reduction in memory consumption. Post place-and-route results show that our architecture demonstrates 1.3x∼1.6x improvment in energy efficiency and 1.5x∼5.3x better memory efficiency compared with the state-of-the-art designs. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only) 16

Re-targeting Optimization Sequences from Scalar Processors t...

引用

proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Ronak Kogta Suresh Purini Ajit Mathew International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781450338561

A high-level synthesis compiler translates a source program written in a high level programming language such as C or SystemC into an equivalent circuit. The performance of the generated circuit in terms of metrics such as area, frequency and clock cycles depends on the compiler optimizations enabled and their order of application. Finding an optimal sequence for a given program is a hard combinatorial optimization problem. In this paper, we propose a practical and search time efficient technique for finding a near-optimal sequence for a given program. The main idea is to strike a balance between the search for a universally good sequence (like that of O3) which works for all programs vis-a-vis finding a good sequence on a per-program basis. Towards that, we construct a rich downsampled sequence set, which caters to different program classes, from the unbounded optimization sequence space by applying heuristic search algorithms on a set of Microkernel benchmark programs. The optimization metric that we use while constructing the downsampled sequence set is the execution time on a scalar processor. Given a new program, we try all the sequences from the downsampled sequence setand pick the best. Applying this technique in the LegUp high-level synthesis compiler, we are able to obtain 23% and 40% improvement on CHStone and Machsuite benchmark programs respectively. We also propose techniques to further reduce the size of the downsampled sequence set to improve the sequence search time.

关键词： high level synthesis optimization compilers

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Optimizing FPGA-based accelerator design for deep convolutional neural networks 15

Optimizing FPGA-based accelerator design for deep convolutio...

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acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Zhang, Chen Li, Peng Sun, Guangyu Guan, Yijin Xiao, Bingjun Cong, Jason Center for Energy-Efficient Computing and Applications Peking University China Computer Science Department University of California Los Angeles United States PKU UCLA Joint Research Institute in Science and Engineering United States

ISBN: (纸本)9781450333153

Convolutional neural network (CNN) has been widely employed for image recognition because it can achieve high accuracy by emulating behavior of optic nerves in living creatures. Recently, rapid growth of modern applications based on deep learning algorithms has further improved research and implementations. Especially, various accelerators for deep CNN have been proposed based on FPGA platform because it has advantages of high performance, reconfigurability, and fast development round, etc. Although current FPGA accelerators have demonstrated better performance over generic processors, the accelerator design space has not been well exploited. One critical problem is that the computation throughput may not well match the memory bandwidth provided an FPGA platform. Consequently, existing approaches cannot achieve best performance due to underutilization of either logic resource or memory bandwidth. At the same time, the increasing complexity and scalability of deep learning applications aggravate this problem. In order to overcome this problem, we propose an analytical design scheme using the rooine model. For any solution of a CNN design, we quantitatively analyze its computing throughput and required memory bandwidth using various optimization techniques, such as loop tiling and transformation. Then, with the help of rooine model, we can identify the solution with best performance and lowest FPGA resource requirement. As a case study, we implement a CNN accelerator on a VC707 FPGA board and compare it to previous approaches. Our implementation achieves a peak performance of 61.62 GFLOPS under 100MHz working frequency, which outperform previous approaches significantly.

关键词： field programmable gate arrays (FPGA)

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The Digital Bidirectional Function as a Hardware Security Primitive: Architecture and Applications 20

The Digital Bidirectional Function as a Hardware Security Pr...

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IEEE/acm international symposium on Low Power Electronics and Design (ISLPED)

作者： Xu, Teng Potkonjak, Miodrag Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA

ISBN: (纸本)9781467380096

Security and low power have emerged to become two essential requirements to modern design. In this paper, we have proposed a new hardware security primitive: digital bidirectional function (DBF) designed on FPGA to meet both criteria. The DBF has two forms of functions and implements two mappings of opposite directions. The DBF can be easily implemented using hierarchical lookup-table (LUT) structures with low delay and power overhead. In terms of applications, we demonstrate how DBF is applied in the protocol of secure message transfer and compare its power/bandwidth consumption with other cryptographic approaches. Our results indicate that the energy consumption of DBF outperforms the traditional ciphers by averagely two to three orders of magnitude.

关键词： DESIGN BASIS FIRES hardware security modern design energy consumption message passing field programmable gate arrays Primitive Bidirectional

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