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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 834 条记录，以下是261-270 订阅

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Delay, power and energy tradeoffs in deep voltage-scaled FPGAs 15

Delay, power and energy tradeoffs in deep voltage-scaled FPG...

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25th Great Lakes symposium on VLSI, GLSVLSI 2015

作者： Abusultan, Monther Khatri, Sunil P. ECE Department Texas A and M University College StationTX77843 United States

ISBN: (纸本)9781450334747

In this paper, we present a circuit-level analysis of deep voltage scaled FPGAs, which operate from full supply to sub-threshold voltages. The logic as well as the interconnect of the FPGA are modeled at the circuit level, and their relative contribution to the delay, power and energy of the FPGA are studied by means of circuit simulations. Three representative designs are studied to explore these design trade-offs. We conclude that the energy and delay-minimal FPGA design is one in which both the interconnect and logic are curtailed from scaling below a fixed voltage (about 550mV in our experiments). If power is a more important design factor (at the cost of delay), it is beneficial to operate both the logic and interconnect between 300mV and 800mV. Copyright © 2015 acm.

关键词： field programmable gate arrays (FPGA)

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Accelerating machine learning kernel in hadoop using FPGAs 15

Accelerating machine learning kernel in hadoop using FPGAs

引用

15th IEEE/acm international symposium on Cluster, Cloud, and Grid Computing, CCGrid 2015

作者： Neshatpour, Katayoun Malik, Maria Homayoun, Houman Department of Electrical and Computer Engineering George Mason University United States

ISBN: (纸本)9781479980062

Big data applications share inherent characteristics that are fundamentally different from traditional desktop CPU, parallel and web service applications. They rely on deep machine learning and data mining applications. A recent trend for big data analytics is to provide heterogeneous architectures to allow support for hardware specialization to construct the right processing engine for analytics applications. However, these specialized heterogeneous architectures require extensive exploration of design aspects to find the optimal architecture in terms of performance and cost. % Considering the time dedicated to create such specialized architectures, a model that estimates the potential speedup achievable through offloading various parts of the algorithm to specialized hardware would be necessary. This paper analyzes how offloading computational intensive kernels of machine learning algorithms to a heterogeneous CPU+FPGA platform enhances the performance. We use the latest Xilinx Signboards for implementation and result analysis. Furthermore, we perform a comprehensive analysis of communication and computation overheads such as data I/O movements, and calling several standard libraries that can not be offloaded to the accelerator to understand how the speedup of each application will contribute to its overall execution in an end-to-end Hadoop MapReduce environment. © 2015 IEEE.

关键词： field programmable gate arrays (FPGA)

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Architecting to Achieve a Billion Requests Per Second Throughput on a Single Key-Value Store Server Platform 15

Architecting to Achieve a Billion Requests Per Second Throug...

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acm/IEEE 42nd Annual international symposium on Computer Architecture (ISCA)

作者： Li, Sheng Lim, Hyeontaek Lee, Victor W. Ahn, Jung Ho Kalia, Anuj Kaminsky, Michael Andersen, David G. Seongil, O. Lee, Sukhan Dubey, Pradeep Intel Labs Santa Clara CA 95054 USA Carnegie Mellon Univ Pittsburgh PA 15213 USA Seoul Natl Univ Seoul 151 South Korea

ISBN: (纸本)9781450334020

Distributed in-memory key-value stores (KVSs), such as memcached, have become a critical data serving layer in modern Internet-oriented datacenter infrastructure. Their performance and efficiency directly affect the QoS of web services and the efficiency of datacenters. Traditionally, these systems have had significant overheads from inefficient network processing, OS kernel involvement, and concurrency control. Two recent research thrusts have focused upon improving key-value performance. Hardware-centric research has started to explore specialized platforms including FPGA5 for KVSs;results demonstrated an order of magnitude increase in throughput and energy efficiency over stock memcached. Software-centric research revisited the KVS application to address fundamental software bottlenecks and to exploit the full potential of modern commodity hardware;these efforts too showed orders of magnitude improvement over stock memcached. We aim at architecting high performance and efficient KVS platforms, and start with a rigorous architectural characterization across system stacks over a collection of representative KVS implementations. Our detailed full-system characterization not only identifies the critical hardware/software ingredients for high-petformance KVS systems, but also leads to guided optimizations atop a recent design to achieve a record setting throughput of 120 million requests per second (MRPS) on a single commodity server. Our implementation delivers 9.2X the performance (RPS) and 2.8X the system energy efficiency (RPS/watt) of the best-published FPGA-based claims. We craft a set of design principles for future platform architectures, and via detailed simulations demonstrate the capability of achieving a billion RPS with a single server constructed following our principles.

关键词： field programmable gate arrays (FPGA)

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Acceleration of Synthetic Aperture Radar (SAR) Algorithms using field programmable gate arrays (FPGAs) (Abstract Only) 15

Acceleration of Synthetic Aperture Radar (SAR) Algorithms us...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Youngsoo Kim William Harding Clay S. Gloster Winser Alexander North Carolina A&T State University Greensboro NC USA North Carolina State University Raleigh NC USA

ISBN: (纸本)9781450333153

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, field programmable gate arrays (FPGAs) can be used to house hardware-based custom implementations of these kernels to speed up these applications. In this paper, we demonstrate a methodology for algorithm acceleration. We used SAR as a case study to illustrate the tremendous potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show an average speed-up of 188 when using the FPGA-based hardware accelerator as opposed to using a software implementation running on a typical general purpose processor.

关键词： floating point fpga logarithmic synthetic aperture radar homomorphic

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An Automated Design Framework for Floating Point Scientific Algorithms using field programmable gate arrays (FPGAs) (Abstract Only) 15

An Automated Design Framework for Floating Point Scientific ...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Michaela E. Amoo Youngsoo Kim Vance Alford Shrikant Jadhav Naser I. El-Bathy Clay S. Gloster Jr. Howard University Washington DC USA North Carolina A&T State University Greensboro NC USA

ISBN: (纸本)9781450333153

This paper presents a reconfigurable computing environment while addressing the problem of porting High Performance Computing (HPC) applications directly to field programmable gate arrays (FPGAs)-based architectures. The objectives of this research are developing a comprehensive floating point library of essential functions for scientific applications; demonstrate order of magnitude speedup of reconfigurable computing applications, demonstrating the effectiveness of automated design framework for both development and test of scientific algorithms. The developed framework can be reused in various scientific applications which shares kernel functions. The study of this research has identified an exponential function as a kernel for cellular ophthalmoscopy camera processing, traffic monitoring and light wave simulation. The paper demonstrates 30x speedup of these kernels in three algorithms using its novel architecture and its automated toolset. Exponential kernel generation case study and its flexible hardware implementation on an FPGA has been validated onto a Xilinx LX-100 device and the Nallatech H101-PCIXM FPGA board.

关键词： floating point exponential hpc fpga

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FPGA'12 - proceedings of the 2012 acm/sigda international symposium on field programmable gate arrays

FPGA'12 - Proceedings of the 2012 ACM/SIGDA International Sy...

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2012 acm/sigda international symposium on field programmable gate arrays, FPGA'12

ISBN: (纸本)9781450311557

The proceedings contain 36 papers. The topics discussed include: speedy FPGA-based packet classifiers with low on-chip memory requirements;a real-time stereo vision system using a tree-structured dynamic programming on FPGA;incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation;communication visualization for bottleneck detection of high-level synthesis applications;a mixed precision Monte Carlo methodology for reconfigurable accelerator systems;saturating the transceiver bandwidth: switch fabric design on FPGAs;saturating the transceiver bandwidth: switch fabric design on FPGAs;limit study of energy & delay benefits of component-specific routing;impact of FPGA architecture on resource sharing in high-level synthesis;and securing netlist-level FPGA design through exploiting process variation and degradation.

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Logic gates in the routing network of FPGAs (Abstract Only) 15

Logic Gates in the routing network of FPGAs (Abstract Only)

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Elias Vansteenkiste Berg Severens Dirk Stroobandt Ghent University Ghent Belgium

ISBN: (纸本)9781450333153

We propose a new kind of FPGA architecture with a routing network that not only provides interconnections between the functional blocks but also performs some logic operation. More specifically we replaced the routing multiplexer node in the conventional architecture with an element that can be used as both AND gate and multiplexer. A conventional routing multiplexer node consists of a multiplexer and a two stage buffer. In our new architecture a NAND gate replaces the first inverter stage of the buffer and two multiplexers half the size of the original multiplexer replace the original multiplexer. The aim of this study is to determine if this kind of architecture is feasible and if it is worth to implement pack, placement and routing tools in the future. We developed a new technology-mapping algorithm and sized the transistors in this new architecture to evaluate the area and delay. Preliminary results indicate that the gain in logic depth and area achieved by mapping to not only LUTs but also to AND gates outweighs the overhead of introducing AND gates in the routing network with a net reduction in area-delay product of 5.6. Designs implemented on the proposed architecture would require 11.2 % more area, but they will have a 14 % decreased logic depth and the architecture has a slightly faster representative critical path. These results are preliminary because the pack, place and route routines are not implemented yet.

关键词： transistor sizing technology mapping routing nodes programmable interconnection architecture logic gates

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FiT: An Automated Toolkit for Matching Processor Architecture to Applications (Abstract Only) 15

FiT: An Automated Toolkit for Matching Processor Architectur...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Charles Mutigwe Johnson Kinyua Farhad Aghdasi NxCORES Research East Longmeadow MA USA Virginia International University Fairfax VA USA University of Fort Hare Alice South Africa

ISBN: (纸本)9781450333153

As the complexity of designing electronic systems continues to grow, the most commonly used solution has been to move the design process to higher levels of abstraction via software tools. In this work we present one such tool that can be used to automatically generate custom processors and systems-on-chip (SoC) from C source code or application binary files, with no requirement for the user to understand any of the underlying hardware systems. This tool also does not call for the application to be profiled for any 'hot spots' as a prerequisite for generating the custom processor. We use the toolkit to generate two types of custom processors; the area-optimized processors and the performance-optimized processors. We study the resource utilization of the custom processors and compare them with those predicted by the core density model. We find that the performance-optimized processor results are as predicted by the core density model.

关键词： electronic system level (esl) design application-specific soft processor reconfigurable computing c-to-silicon compiler

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Quantifying the cost and benefit of latency insensitive communication on FPGAs 14

Quantifying the cost and benefit of latency insensitive comm...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Murray, Kevin E. Betz, Vaughn Dept. of Electrical and Computer Engineering University of Toronto Ontario Canada

ISBN: (纸本)9781450326711

Latency insensitive communication oers many potential benets for FPGA designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to understand the costs and trade-os associated with any new design style. This paper presents optimized implementations of latency insensitive communication building blocks, quanties their overheads in terms of area and frequency, and provides guidance to designers on how to generate high-speed and areae cient latency insensitive systems.

关键词： field programmable gate arrays (FPGA)

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A power side-channel-based digital to analog converter for xilinx FPGAs 14

A power side-channel-based digital to analog converter for x...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Hutchings, Brad L. Monson, Joshua Savory, Danny Keeley, Jared Department of Electrical and Computer Engineering Brigham Young University Provo UT United States

ISBN: (纸本)9781450326711

A novel Digital to Analog Converter (DAC) modulates the overall power consumption of an FPGA by disabling/enabling short circuits programmed into the interconnect. The power pin of the FPGA serves as the output of the DAC. The DAC achieves high linearity and can be used to implement applications in communications, security, etc. The shortcircuit-based DAC consumes 1/3 the area of an alternative shift-register-based DAC that is presented for the sake of comparison.

关键词： field programmable gate arrays (FPGA)

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