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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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A soft error vulnerability analysis framework for xilinx FPGAs 14

A soft error vulnerability analysis framework for xilinx FPG...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Sari, Aitzan Agiakatsikas, Dimitris Psarakis, Mihalis Department of Informatics University of Piraeus Greece

ISBN: (纸本)9781450326711

Today's SRAM-based FPGAs provide a reach set of computing resources which makes them attractive in demanding and critical application domains, such as avionics and space. Unfortunately, their high reliance on SRAM configuration memory arise reliability issues due to the single-event upsets (SEUs). Considering the criticality of these applications, the vulnerability analysis of FPGA designs to SEUs becomes essential part of the design flow. In this context, we present an open-source framework for the soft error vulnerability analysis of Xilinx FPGA devices. The proposed framework will allow researchers to evaluate their reliability-aware CAD algorithms and estimate the soft error susceptibility of the designs at early stages of the implementation flow for the latest Xilinx architectures.

关键词： field programmable gate arrays (FPGA)

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A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only) 15

A Mixed-Grained Reconfigurable Computing Platform for Multip...

引用

proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Leibo Liu Yingjie Chen Dong Wang Min Zhu Shouyi Yin Shaojun Wei Tsinghua University Beijing China Beijing Jiaotong University Beijing China

ISBN: (纸本)9781450333153

A mixed-grained reconfigurable computing platform targeting multiple-standard video decoding is proposed in this paper. The platform integrates eight coarse-grained Reconfigurable Processing Units (RPUs), each of which consists of 16×16 multi-functional Processing Elements (PEs) and are implemented in TSMC 65 nm technology and two Altera Stratix IV EP4SE820 FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including H.264, MPEG-2, AVS and HEVC. Two types of platform configuration are tested in this work. One configuration utilizes two RPUs and targets multiple-standard high-definition (HD) video decoding, while the other utilizes only one RPU, which works under a lower frequency and targets at standard resolution (SD) decoding. The HD configuration can decode 1920×1080 H.264 video streams at 30 frames per second (fps) under 200 MHz and 1920×1080 HEVC video streams at 30 fps under 236 MHz. It achieves a 25% performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 3.85× performance boosts over the Intel i5 general-purpose CPU for HEVC decoding.

关键词： field-programmable gate array coarse-grained reconfigurable array video decoding reconfigurable computing

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Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics (Abstract Only) 15

Architecture of Reconfigurable-Logic Cell Array with Atom Sw...

引用

proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Xu Bai Yukihide Tsuji Ayuka Morioka Makoto Miyamura Toshi Sakamoto Munehiro Tada Naoki Banno Koichiro Okamoto Noriyuki Iguchi Hiromitsu Hada Low-power Electronics Association & Project (LEAP) Tsukuba Japan

ISBN: (纸本)9781450333153

Emerging nonvolatile memories (NVMs) have a potential to overcome the issues in the conventional static random-access memory (SRAM) based reconfigurable logic cell arrays (RLCAs). Replacing a CMOS switch element composed of a SRAM and a pass transistor by a NVM reduces chip size. And non-volatility reduces the stand-by power. More importantly, the compactness of NVM allows fine-grain logic cells (small cluster size), which advantageously enables a highly efficient cell usage, resulting in compact circuit for applications. In this paper, we investigate the fine-grain cell architecture using atom switch which is one of the NVMs. We evaluate the effect of the cluster size and the segment length on the atom-switch-based RLCA to confirm the optimal point considering area-delay product. Cluster size is optimized to be 4, which is smaller than that in the conventional SRAM- and multiplexer-based RLCA. This optimization is originated from the fact that the inter-delay among clusters is only twice of the intra-delay in cluster for atom-switch-based RLCA with routing block formed by crossbar switches because of very small capacitance and resistance of atom switches. On the other hand, the segment length is optimized to be 4, which is the same as that in the conventional SRAM- and multiplexer-based RLCA.

关键词： programmable logic routing fabrics cross bar switch atom switch cluster nonvolatile

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Dynamic voltage & frequency scaling with online slack measurement 14

Dynamic voltage & frequency scaling with online slack measur...

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Levine, Joshua M. Stott, Edward Cheung, Peter Y. K. Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (纸本)9781450326711

Timing margins in FPGAs are already significant and as process scaling continues they will have to grow to guarantee operation under increased variation. Margins enforce worst-case operation even in typical conditions and result in devices operating more slowly and consuming more energy than necessary. This paper presents a method of dynamic voltage and frequency scaling that uses online slack measurement to determine timing headroom in a circuit while it is operating and scale the voltage and/or frequency in response. Doing so can significantly reduce power consumption or increase throughput with a minimal overhead. The method is demonstrated on a number of benchmark circuits under a range of operating conditions, constraints and optimisation targets.

关键词： field programmable gate arrays (FPGA)

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Accelerating frequent item counting with FPGA 14

Accelerating frequent item counting with FPGA

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Sun, Yuliang Wang, Zilong Huang, Sitao Wang, Lanjun Wang, Yu Luo, Rong Yang, Huazhong E.E. Dept. TNLIST Tsinghua University China IBM Research-China China

ISBN: (纸本)9781450326711

Frequent item counting is one of the most important operations in time series data mining algorithms, and the space saving algorithm is a widely used approach to solving this problem. With the rapid rising of data input speeds, the most challenging problem in frequent item counting is to meet the requirement of wire-speed processing. In this paper, we propose a streaming oriented PE-ring framework on FPGA for counting frequent items. Compared with the best existing FPGA implementation, our basic PE-ring framework saves 50% lookup table resources cost and achieves the same throughput in a more scalable way. Furthermore, we adopt SIMD-like cascaded filter for further performance improvements, which outperforms the previous work by up to 3.24 times in some data distributions.

关键词： field programmable gate arrays (FPGA)

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Computation-in-memory based parallel adder

Computation-in-memory based parallel adder

引用

IEEE international symposium on Nanoscale Architectures (NANOARCH)

作者： Hoang Anh Du Nguyen Lei Xie Mottaqiallah Taouil Razvan Nane Said Hamdioui Koen Bertels Laboratory of Computer Engineering Faculty of EE Mathematics and CS Delft University of Technology Delft Zuid-Holland NL Laboratory of Computer Engineering Faculty of EE Mathematics and CS Delft University of Technology Delft CD The Netherlands

Today's computing systems suffer from memory/communication bottleneck, resulting in energy and performance inefficiency. This makes them incapable to solve data-intensive applications within economically acceptable limits. Computation-In-Memory (CIM) architecture, based on the integration of storage and computation in the same physical location using non-volatile memristor technology offers a potential solution for the memory bottleneck. This paper presents a CIM based parallel adder, and shows its potentials and superiority for intensive computing and massive parallelism by comparing it with state-of-the art computing systems including multicore, GPU and FPGA architecture. The results show that CIM based parallel adder can achieve at least two orders of magnitude improvement in computational efficiency, energy efficiency and area efficiency.

关键词： Adders Computer integrated manufacturing Graphics processing units Multicore processing field programmable gate arrays Delays

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A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory arrays (Abstract Only) 15

A Hardware Implementation of a Unit for Geometric Algebra Op...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Gerardo Soria García Adrian Pedroza de la Cruz Susana Ortega Cisneros Juan José Raygoza Panduro Eduardo Bayro Corrochano Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional Zapopan Mexico Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional zapopan Mexico Universidad de Guadalajara Guadalajara Mexico

ISBN: (纸本)9781450333153

Geometric algebra (GA) is a powerful and versatile mathematical tool which helps to intuitively express and manipulate complex geometric relationships. It has recently been used in engineering problems such computer graphics, machine vision, robotics, among others. The problem with GA in its numeric version is that it requires many arithmetic operations, and the length of the input vectors is unknown until runtime in a generic architecture operating over homogeneous elements. Few works in hardware architectures for GA were developed to improve the performance in GA applications. In this work, a hardware architecture of a unit for GA operations (geometric product) for FPGA is presented. The main contribution of this work is the use of parallel memory arrays with access conflict avoidance for dealing with the issue of unknown length of input/output vectors, the intention is to reduce memory wasted when storing the input and output vectors. In this first stage of the project, we have implemented only a single access function (fixed-length) in the memory array in order to test the core of geometric product. In future works we will implement a full set of access functions with different lengths and shapes. In this work, only the simulations are presented; in the future, we will also present the experimental results

关键词： fpga address generator geometric product. geometric algebra memory arrays

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OmpSs@zynq all-programmable soc ecosystem

OmpSs@zynq all-programmable soc ecosystem

引用

2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Filgueras, Antonio Gil, Eduard Jimenez-Gonzalez, Daniel Alvarez, Carlos Martorell, Xavier Langer, Jan Noguera, Juanjo Vissers, Kees Barcelona Supercomputing Center Spain Universitat Politecnica de Catalunya Spain Xilinx Research Lab United States

ISBN: (纸本)9781450326711

OmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely inuenced the recently appeared OpenMP 4.0 specication. Zynq All-programmable SoC combines the features of a SMP and a FPGA and benets DLP, ILP and TLP parallelisms in order to eciently exploit the new tech-nology improvements and chip resource capacities. In this paper, we focus on programmability and heterogeneous ex-ecution support, presenting a successful combination of the OmpSs programming model and the Zynq All-programmable SoC platforms.

关键词： System-on-chip

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FPGA place & route challenges 14

FPGA place & route challenges

引用

2014 acm international symposium on Physical Design, ISPD 2014

作者： Aggarwal, Rajat Xilinx Inc 2100 Logic Dr San Jose CA 95124 United States

In this paper, we describe the challenges that Place and Route tools face to implement the user designs on modern FPGAs while meeting the timing and power constraints.

ISBN: (纸本)9781450325929

In this paper, we describe the challenges that Place and Route tools face to implement the user designs on modern FPGAs while meeting the timing and power constraints.

关键词： field programmable gate arrays (FPGA)

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Rent's rule based FPGA packing for routability optimization 14

Rent's rule based FPGA packing for routability optimization

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Feng, Wenyi Greene, Jonathan Vorwerk, Kristofer Pevzner, Val Kundu, Arun Microsemi Corporation 3870 N 1st Street San Jose CA 95134 United States

ISBN: (纸本)9781450326711

Packing is a critical step in the CAD flow for cluster-based FPGA architectures, and has a significant impact on the quality of the final placement and routing results. One basic quality metric is routability. Traditionally, minimizing cut (the number of external signals) has been used as the main criterion in packing for routability optimization. This paper shows that minimizing cut is a sub-optimal criterion, and argues to use the Rent characteristic as the new criterion for FPGA packing. We further propose using a recursive bipartitioning-based k-way partitioner to optimize the Rent characteristic during packing. We developed a new packer, PPack2, based on this approach. Compared to T-VPack, PPack2 achieves 35.4%, 35.6%, and 11.2% reduction in wire length, minimal channel width, and critical path delay, respectively. These improvements show that PPack2 outperforms all previous leading packing tools (including iRAC, HDPack, and the original PPack) by a wide margin.

关键词： field programmable gate arrays (FPGA)

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