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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 834 条记录，以下是291-300 订阅

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MogaMap and DynPack: Multi-Objective mapping and packing algorithms for optimization of area, performance and power consumption in FPGAs 14

MogaMap and DynPack: Multi-Objective mapping and packing alg...

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27th symposium on Integrated Circuits and Systems Design, SBCCI 2014

作者： Souza, V.L. Silva-Filho, A.G. Federal University of Pernambuco Recife Brazil

ISBN: (纸本)9781479968732

This paper presents a new technology mapper, MogaMap. The mapper is based on a hybrid approach that uses evolutionary algorithm associated with specific heuristics of the problem in order to find better trade-off results among area, performance and power consumption. Besides that, we present DynPack, a multi-objective clustering tool based on net connections and cluster dynamic status. MogaMap and DynPack have been integrated into VTR and, the pos-route analysis shows that, on average, our technique is able to reduce the number of complex block logics by 8%, the critical path delay by 16% and the power consumption by 15% when compared to state-of-the- art. © 2014 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services

A Reconfigurable Fabric for Accelerating Large-Scale Datacen...

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acm/IEEE 41st Annual international symposium on Computer Architecture (ISCA)

作者： Putnam, Andrew Caulfield, Adrian M. Chung, Eric S. Chiou, Derek Constantinides, Kypros Demme, John Esmaeilzadeh, Hadi Fowers, Jeremy Gopal, Gopi Prashanth Gray, Jan Haselman, Michael Hauck, Scott Heil, Stephen Hormati, Amir Kim, Joo-Young Lanka, Sitaram Larus, James Peterson, Eric Pope, Simon Smith, Aaron Thong, Jason Xiao, Phillip Yi Burger, Doug Microsoft Corp Redmond WA 98052 USA

ISBN: (纸本)9781479943944

Datacenter workloads demand high computational capabilities, flexibility power efficiency and low cost. Ir is challenging to improve all of these factors simultaneously To advance data-center capabilities beyond what commodity server designs can provide, we have designed and built a composable, reconfigurable fabric to accelerate portions of large-scale software services. Each instantiation of the fabric consists of a 6x8 2-D torus of high-end Stratix V FPGAs embedded into a half-rack of 48 machines. One FPGA is placed into each server;accessible through PCIe, and wired directly to other FPGAs with pairs of 10 Gb MS cables. In this paper, we describe a medium-scale deployment of this fabric on a bed of 1,632 servers, and measure its efficacy in accelerating the Bing web search engine. We describe the requirements and architecture of the system, detail the critical engineering challenges and solutions needed to make the system robust in the presence of failures, and measure the performance, power;and resilience of the system when ranking candidate documents. Under high load, the large-scale reconfigurable fabric improves the ranking throughput of each server by a factor of 95% for a fixed latency distribution-or;while maintaining equivalent throughput, reduces the tail latency by 29%.

关键词： field programmable gate arrays (FPGA)

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Adaptive Raytracing Implementation using Partial Dynamic Reconfiguration 28

Adaptive Raytracing Implementation using Partial Dynamic Rec...

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28th IEEE international Parallel & Distributed Processing symposium Workshops (IPDPSW)

作者： Durelli, Gianluca Spada, Fabrizio Cattaneo, Riccardo Pilato, Christian Pau, Danilo Santambrogio, Marco D. Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy Columbia Univ Dept Comp Sci New York NY 10027 USA ST Microelect Milan Italy

ISBN: (纸本)9781479941162

The continuous strive for improvements in visual realism is progressively increasing the complexity of algorithms for simulating light physics to produce very realistic scenes. As a result, they are becoming more and more suitable for hardware acceleration, even if they introduce new challenges due to the high requirements in terms of resources. In this paper we propose a hardware implementation of the raytracing algorithm, which is a method for rendering 3D scenes. We exploit partial dynamic reconfiguration to adapt the hardware to the specific part of the image under analysis. This allows us to obtain up to 30% better performance with respect to the software baseline implementation on the AVNET ZedBoard platform.

关键词： field programmable gate arrays Embedded software Image processing

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PaRA-Sched: a Reconfiguration-Aware Scheduler for Reconfigurable Architectures 28

PaRA-Sched: a Reconfiguration-Aware Scheduler for Reconfigur...

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28th IEEE international Parallel & Distributed Processing symposium Workshops (IPDPSW)

作者： Cattaneo, Riccardo Bellini, Riccardo Durelli, Gianluca Pilato, Christian Santambrogio, Marco D. Sciuto, Donatella Politecn Milan Dipartimento Elettron & Informaz Milan Italy Columbia Univ Dept Comp Sci New York NY 10027 USA

ISBN: (纸本)9781479941162

Harnessing the full capabilities offered by reconfigurable hardware is still a demanding task: the lack of proper methodologies and the intrinsic time consuming and error prone tailoring of these systems around the specific application places a barrier to the adoption of this technology. Partial and Dynamic Reconfiguration (PDR), in this context, is a specific feature whose potential is undiscussed but yet to uncover. In this work, we propose PaRA-Sched, an improvement for a state of the art, highly automated design methodology that allows the designer to rapidly explore the impact of PDR employment during the early stages of the design process. Specifically, we extend the scheduling infrastructure of the framework to explicitly take into account PDR to better explore the design space and improve overall performance by automatically masking reconfiguration time when possible. We show how this additional degree of freedom leads to designs whose performance are improved with respect to the baseline, with a limited increase in time spent during DSE.

关键词： field programmable gate arrays High Performance Computing Reconfigurable Architectures Scheduling algorithms Design methodology

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An efficient parallel yet pipelined reconfigurable architecture for M-PLN Weightless Neural Networks 14

An efficient parallel yet pipelined reconfigurable architect...

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27th symposium on Integrated Circuits and Systems Design, SBCCI 2014

作者： Da Silva, Felipe P. De Sa, Alan Oliveria Nedjahz, Nadia De Macedo Mourelle, Luiza Postgraduate Program of Electronics Engineering Faculty of Engineering State University of Rio de Janeiro Rio de Janeiro Brazil Dept. of Electronics Engineering and Telecommunications Faculty of Engineering State University of Rio de Janeiro Rio de Janeiro Brazil Brasil PCH Brazil Brazilian Navy Center of Elec-tronics Communications and Information Technology Rio de Janeiro RJ Brazil

ISBN: (纸本)9781479968732

Weightless Neural Networks (WNNs) are a powerful mechanism for pattern recognition. Aiming at enhancing their learning capabilities, Multivalued Probabilistic Logic Neurons (M-PLN) are used, instead of crisp neurons with a 0/1 output. An M-PLN bookkeeps a triggering probability for each input pattern to be recognized. The M-PLN model attempts to strengthen the discrepancies between distinct patterns used during the training process and those that have not yet been processed. In this paper, an efficient yet customizable hardware architecture for M-PLN based WNN is proposed. It implements the structure and learning process of a weightless pyramidal WNN, augmented by a probabilistic rewarding/punishing search algorithm. The training algorithm can adapt itself to the overall hit ratio so far achieved by the network. Using class-dedicated layers, the hardware is able to handle image classification in parallel and thus, very efficiently. Furthermore, the classification process is performed in a pipelined manner so its stages never stop working until all input images are classified. Nonetheless, only one of these layers is active during network training. Last but not least, the architecture is customizable as its structure can be tailored in accordance to the application characteristics. It was modeled and functionally tested. Estimated time requirements based on many simulations are reported. The architecture exhibits performance and reconfiguration capabilities that are very promising and encouraging towards the synthesis of a prototype. © 2014 IEEE.

关键词： field programmable gate arrays (FPGA)

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[email protected] all-programmable SoC ecosystem 14

[email protected] all-programmable SoC ecosystem

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proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Antonio Filgueras Eduard Gil Daniel Jimenez-Gonzalez Carlos Alvarez Xavier Martorell Jan Langer Juanjo Noguera Kees Vissers Barcelona Supercomputing Center - BSC-CNS Barcelona Spain Universitat Politecnica de Catalunya - UPC Barcelona Spain Xilinx Inc. Dublin Ireland Xilinx inc. San Jose CA USA

ISBN: (纸本)9781450326711

OmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely influenced the recently appeared OpenMP 4.0 specification. Zynq All-programmable SoC combines the features of a SMP and a FPGA and benefits DLP, ILP and TLP parallelisms in order to efficiently exploit the new technology improvements and chip resource capacities. In this paper, we focus on programmability and heterogeneous execution support, presenting a successful combination of the OmpSs programming model and the Zynq All-programmable SoC platforms.

关键词： task dataflow models automatic hardware generation framework heterogenous parallel programming model

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Methodology to generate multi-dimensional systolic arrays for FPGAs using openCL (abstract only) 14

Methodology to generate multi-dimensional systolic arrays fo...

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proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Nick Ni Embedded Applications Engineer Altera Corporation San Jose CA USA

ISBN: (纸本)9781450326711

Systolic arrays (SA) in a FPGA provide a significant speed up on many scientific calculations through massive parallelism exploitation. The low-level hardware design of such complex SA is becoming more time-consuming and non-scalable with more transistors being available on a single chip. In this paper we present a novel methodology to generate multi-dimensional SA for FPGAs using a well-accepted high-level language, OpenCL. Kernels written in OpenCL can then be compiled directly into hardware using an OpenCL high-level synthesis tool. A complex case study using our methodology is presented. We were able to design, generate, verify and optimize the entire FPGA based hardware accelerator using the Smith-Waterman, in only three man weeks. The accelerator's top performance was 32.6 GCUPS (Giga-Cell-Updates-Per-Second) on a DNA similarity search with 1.3 GCUPS/watt efficiency. The result is superior to most state-of-the-art CPU/GPU implementations and competitive against a hand-crafted hardware design which took many months to develop.

关键词： high-level synthesis bioinformatics productivity smith-waterman opencl fpga systolic arrays generation algorithm

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Improving bitstream compression by modifying FPGA architecture 13

Improving bitstream compression by modifying FPGA architectu...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Razavi, Seyyed Ahmad Saheb Zamani, Morteza Department of Computer Engineering and Information Technology Amirkabir University of Technology Tehran Iran

ISBN: (纸本)9781450318877

The size of configuration bitstreams of field-programmable gate arrays (FPGA) is increasing rapidly. Compression techniques are used to decrease the size of bitstreams. In this paper, an appropriate bitstream format and variable symbol lengths are proposed to utilize the routing patterns for enhancing the compression efficiency. An order of inputs of multiplexers in switch modules is also proposed to improve the symbol statistics and hence, the compression efficiency. A framework to generate the bitstream and hardware description of FPGAs is developed as well. Experimental results over 20 MCNC benchmarks show that by applying the proposed approaches, the compression rate is improved by 46% on average compared to the methods with fixed symbol lengths without any area and performance degradation. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Location, location, location - The role of spatial locality in asymptotic energy minimization 13

Location, location, location - The role of spatial locality ...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： DeHon, André M. Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450318877

Locality exploitation is essential to asymptotic energy minimization for gate array netlist evaluation. Naive implementations that ignore locality, including flat crossbars and simple processors based on monolithic memories, can require O(N2) energy for an N node graph. Specifically, it is important to exploit locality (1) to reduce the size of the description of the graph, (2) to reduce data movement, and (3) to reduce instruction movement. FPGAs exploit all three. FPGAs with a Rent Exponent p © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Faithful single-precision floating-point tangent for FPGAs 13

Faithful single-precision floating-point tangent for FPGAs

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Langhammer, Martin Pasca, Bogdan Altera European Technology Centre High Wycombe United Kingdom

ISBN: (纸本)9781450318877

This paper presents an FPGA-specific implementation of the floating-point tangent function. The implementation inputs values in the interval [-π/2,π/2], targets the IEEE-754 single-precision format and has an accuracy of 1 ulp. The proposed work is based on a combination of mathematical identities and properties of the tangent function in floating point. The architecture was designed having the {Stratix-IV} DSP and memory blocks in mind but should map well on any contemporary FPGA featuring embedded multiplier and memory blocks. It outperforms generic polynomial approximation targeting the same resource spectrum and provides better resources trade-offs than classical CORDIC-based *** presented work is widely available as being part of the Altera DSP Builder Advanced Blockset. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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