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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Area-efficient near-associative memories on FPGAs 13

Area-efficient near-associative memories on FPGAs

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Dhawan, Udit DeHon, André Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450318877

Associative memories can map sparsely used keys to values with low latency but can incur heavy area overheads. The lack of customized hardware for associative memories in today's mainstream FPGAs exacerbates the overhead cost of building these memories using the fixed address match BRAMs. In this paper, we develop a new, FPGA-friendly, memory architecture based on a multiple hash scheme that is able to achieve near-associative performance (less than 5% of evictions due to conflicts) without the area overheads of a fully associative memory on FPGAs. Using the proposed architecture as a 64KB L1 data cache, we show that it is able to achieve near-associative miss-rates while consuming 6-7× less FPGA memory resources for a set of benchmark programs from the SPEC2006 suite than fully associative memories generated by the Xilinx Coregen tool. Benefits increase with match width, allowing area reduction up to 100×. At the same time, the new architecture has lower latency than the fully associative memory - 3.7 ns for a 1024-entry flat version or 6.1 ns for an area-efficient version compared to 8.8 ns for a fully associative memory for a 64b key. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Fully-functional FPGA prototype with fine-grain programmable body biasing 13

Fully-functional FPGA prototype with fine-grain programmable...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Hioki, Masakazu Sekigawa, Toshihiro Nakagawa, Tadashi Koike, Hanpei Matsumoto, Yohei Kawanami, Takashi Tsutsumi, Toshiyuki Tsukuba Japan Tokyo University of Marine Science and Technology Tokyo Japan Kanazawa Institute of Technology Kanazawa Japan Meiji University Kawasaki Japan

ISBN: (纸本)9781450318877

A fully-functional FPGA prototype chip in which the programmable body bias voltage can be individually applied to elemental circuits such as MUXes, LUT and DFF is fabricated using low-power 90-nm bulk CMOS technology and the area overhead, dynamic current, static current and operational speed are evaluated in silicon. In measurements, 10 ISCAS benchmark circuits are implemented by employing newly developed CAD tools which consist of VT mapper as well as placer and router. Mask layout shows that well-separated margins, programmable body bias circuits, and additional configuration memories occupy 54% of the FPGA tile area. Measurement results show that the fabricated FPGA reduces the static current by 91.4% in average. In addition, evaluations by implementing ring oscillator with various body bias voltage pairs demonstrate the static current reduction from 23.1 uA to 1.0 uA by assigning low threshold voltage and high threshold voltage to MOSFETs on a critical path and the rest of the MOSFETs, respectively while maintaining the same oscillation frequency of 6.6 MHz as the frequency when all MOSFETs are assigned low threshold voltage. Moreover the fine-grain programmable body bias technique accelerates the oscillation frequency of ring oscillator implemented on FPGA by aggressively applying forward body bias voltage, while assignment of HVT to MOSFETs on the non-critical path by applying the reverse body biasing effectively suppresses exponential increase of static current caused by the forward body biasing. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Video-rate stereo matching using Markov random field TRW-S inference on a hybrid CPU+FPGA computing platform 13

Video-rate stereo matching using Markov random field TRW-S i...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Choi, Jungwook Rutenbar, Rob A. Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign 201 N. Goodwin Avenue Urbana IL 61801-2302 United States Department of Computer Science University of Illinois at Urbana-Champaign 201 N. Goodwin Avenue Urbana IL 61801-2302 United States

ISBN: (纸本)9781450318877

We demonstrate a video-rate stereo matching system implemented on a hybrid CPU+FPGA platform (Convey HC-1). Emerging applications such as 3D gesture recognition and automotive navigation demand fast and high quality stereo vision. We describe a custom hardware-accelerated Markov Random field inference system for this task. Starting from a core architecture for streaming tree-reweighted message passing (TRW-S) inference, we describe the end-to-end system engineering needed to move from this single frame message update to full stereo video. We partition the stereo matching procedure across the CPU and the FPGAs, and apply both function-level pipelining and frame-level parallelism to achieve the required speed. Experimental results show that our system achieves a speed of 12 frames per second for challenging video stereo matching tasks. We note that this appears to be the first implementation of TRW-S inference at video rates, and that our system is also significantly faster than several recent GPU implementations of similar stereo inference methods based on belief propagation (BP). © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Accelerating subsequence similarity search based on dynamic time warping distance with FPGA 13

Accelerating subsequence similarity search based on dynamic ...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Wang, Zilong Huang, Sitao Wang, Lanjun Li, Hao Wang, Yu Yang, Huazhong E.E. Dept. TNLIST Tsinghua University Beijing China IBM Research China Beijing China

ISBN: (纸本)9781450318877

Subsequence search, especially subsequence similarity search, is one of the most important subroutines in time series data mining algorithms, and there is increasing evidence that Dynamic Time Warping (DTW) is the best distance metric. However, in spite of the great effort in software speedup techniques, including early abandoning strategies, lower bound, indexing, computation-reuse, DTW still cost too much time for many applications, e.g. 80% of the total time. Since DTW is a 2-Dimension sequential dynamic search with quite high data dependency, it is hard to use parallel hardware to accelerate it. In this work, we propose a novel framework for FPGA based subsequence similarity search and a novel PE-ring structure for DTW calculation. This framework utilizes the data reusability of continuous DTW calculations to reduce the bandwidth and exploit the coarse-grain parallelism;meanwhile guarantees the accuracy with a two-phase precision reduction. The PE-ring supports on-line updating patterns of arbitrary lengths, and utilizes the hard-wired synchronization of FPGA to realize the fine-grained parallelism. It also achieves flexible parallelism degree to do performance-cost trade-off. The experimental results show that we can achieve several orders of magnitude speedup in accelerating subsequence similarity search compared with the best software and current GPU/FPGA implementations in different datasets. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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High throughput and programmable online trafficclassifier on FPGA 13

High throughput and programmable online trafficclassifier on...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Tong, Da Sun, Lu Matam, Kiran Prasanna, Viktor Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles CA United States

ISBN: (纸本)9781450318877

Machine learning (ML) algorithms have been shown to be effective in classifying the dynamic internet traffic today. Using additional features and sophisticated ML techniques can improve accuracy and can classify a broad range of application classes. Realizing such classifiers to meet high data rates is challenging. In this paper, we propose two architectures to realize complete online traffic classifier using flow-level features. First, we develop a traffic classifier based on C4.5 decision tree algorithm and Entropy-MDL discretization algorithm. It achieves an accuracy of 97.92% when classifying a traffic trace consisting of eight application classes. Next, we accelerate our classifier using two architectures on FPGA. One architecture stores the classifier in on-chip distributed RAM. It is designed to sustain a high throughput. The other architecture stores the classifier in block RAM. It is designed to operate with small hardware footprint and thus built at low hardware cost. Experimental results show that our high throughput architecture can sustain a throughput of 550 Gbps assuming 40 Byte packet size. Our low cost architecture demonstrates a 22% better resource efficiency than the high throughput design. It can be easily replicated to achieve 449 Gbps while supporting 160 input traffic streams concurrently. Both architectures are parameterizable and programmable to support any binary-tree-based traffic classifier. We develop a tool which allows users to easily map a binary-tree-based classifier to hardware. The tool takes a classifier as input and automatically generates the Verilog code for the corresponding hardware architecture. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Word-length optimization beyond straight line code 13

Word-length optimization beyond straight line code

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Boland, David P. Constantinides, George A. Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (纸本)9781450318877

The silicon area benefits that result from word-length optimization have been widely reported by the FPGA community. However, to date, most approaches are restricted to straight line code, or code that can be converted into straight line code using techniques such as loop-unrolling. In this paper, we take the first steps towards creating analytical techniques to optimize the precision used throughout custom FPGA accelerators for algorithms that contain loops with data dependent exit conditions. To achieve this, we build on ideas emanating from the software verification community to prove program termination. Our idea is to apply word-length optimization techniques to find the minimum precision required to guarantee that a loop with data dependent exit conditions will terminate. Without techniques to analyze algorithms containing these types of loops, a hardware designer may elect to implement every arithmetic operator throughout a custom FPGA-based accelerator using IEEE-754 standard single or double precision arithmetic. With this approach, the FPGA accelerator would have comparable accuracy to a software implementation. However, we show that using our new technique to create custom fixed and floating point designs, we can obtain silicon area savings of up to 50% over IEEE standard single precision arithmetic, or 80% over IEEE standard double precision arithmetic, at the same time as providing guarantees that the created hardware designs will work in practice. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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C-to-CoRAM: Compiling perfect loop nests to the portable CoRAM abstraction 13

C-to-CoRAM: Compiling perfect loop nests to the portable CoR...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Weisz, Gabriel Hoe, James C. Computer Science Department Carnegie Mellon University Pittsburgh PA United States Electrical and Computer Engineering Department Carnegie Mellon University Pittsburgh PA United States

ISBN: (纸本)9781450318877

This paper presents initial work on developing a C compiler for the CoRAM FPGA computing abstraction. The presented effort focuses on compiling fixed-bound perfect loop nests that operate on large data sets in external DRAM. As required by the CoRAM abstraction, the compiler partitions source code into two separate implementation components: (1) hardware kernel pipelines to be mapped onto the reconfigurable logic fabric;and (2) control threads that express, in a C-like language, the sequencing and coordination of data transfers between the hardware kernels and external DRAM. The compiler performs optimizations to increase parallelism and use DRAM bandwidth efficiently. It can target different FPGA platforms that support the CoRAM abstraction, either natively in a future FPGA or in soft-logic on today's devices. The CoRAM abstraction provides a convenient high-level compilation target to simplify the task of design optimization and system generation. The compiler is evaluated using three test programs (matrix-matrix multiplication, k-nearest neighbor, and 2D convolution) on the Xilinx ML605 and the Altera DE4. Results show that our compiler is able to target the different platforms and effectively exploit their dissimilar capacities and features. Depending on the application, the compiler-generated implementations achieve performance ranging from a factor of 4 slower to a factor of 2 faster relative to hand-designed implementations, as measured on actual hardware. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: Facilitating black-box analysis using software reverse-engineering 13

Side-channel attacks on the bitstream encryption mechanism o...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Moradi, Amir Oswald, David Paar, Christof Swierczynski, Pawel Horst Görtz Institute for IT-Security Ruhr University Bochum Bochum Germany

ISBN: (纸本)9781450318877

In order to protect FPGA designs against IP theft and related issues such as product cloning, all major FPGA manufacturers offer a mechanism to encrypt the bitstream used to configure the FPGA. From a mathematical point of view, the employed encryption algorithms, e.g., AES or 3DES, are highly secure. However, recently it has been shown that the bitstream encryption feature of several FPGA product lines is susceptible to side-channel attacks that monitor the power consumption of the cryptographic module. In this paper, we present the first successful attack on the bitstream encryption of the Altera Stratix II FPGA. To this end, we reverse-engineered the details of the proprietary and unpublished Stratix II bitstream encryption scheme from the Quartus II software. Using this knowledge, we demonstrate that the full 128-bit AES key of a Stratix II can be recovered by means of side-channel analysis with 30,000 measurements, which can be acquired in less than three hours. The complete bitstream of a Stratix II that is (seemingly) protected by the bitstream encryption feature can hence fall into the hands of a competitor or criminal - possibly implying system-wide damage if confidential information such as proprietary encryption schemes or keys programmed into the FPGA are extracted. In addition to lost IP, reprogramming the attacked FPGA with modified code, for instance, to secretly plant a hardware trojan, is a particularly dangerous scenario for many security-critical applications. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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GROK-LAB: Generating real on-chip knowledge for intra-cluster delays using timing extraction 13

GROK-LAB: Generating real on-chip knowledge for intra-cluste...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Gojman, Benjamin Nalmela, Sirisha Mehta, Nikil Howarth, Nicholas DeHon, André Department of Computer and Information Systems University of Pennsylvania 3330 Walnut Street Philadelphia PA 19104 United States Juniper Networks 10 Technology Park Drive Westford MA 01886 United States Department of Computer Science California Institute of Technology MC 305-16 1200 E. California Blvd. Pasadena CA 91125 United States Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450318877

Timing Extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount and type of process variation that exists in the FPGA. To obtain these delays, Timing Extraction measures, using only resources already available in the FPGA, the delay of a small subset of the total paths in the FPGA. We apply Timing Extraction to the Logic Array Block (LAB) on an Altera Cyclone III FPGA to obtain a view of the delay down to near individual LUT granularity, characterizing components with delays on the order of a few hundred picoseconds with a resolution of ±3.2 ps. This information reveals that the 65 nm process used has, on average, random variation of σ/μ = 4.0% with components having an average maximum spread of 83 ps. Timing extraction also shows that as VDD decreases from 1.2 V to 0.9 V in a Cyclone IV 60 nm FPGA, paths slow down and variation increases from σ/μ = 4.3% to σ/μ = 5.8%, a clear indication that lowering VDD magnifies the impact of random variation. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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An FPGA based parallel architecture for music melody matching 13

An FPGA based parallel architecture for music melody matchin...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Wang, Hao Liu, Jyh-Charn Department of Computer Science and Engineering Texas A and M University College Station TX 77840 United States

ISBN: (纸本)9781450318877

We propose an FPGA-based high performance parallel architecture for music retrieval through singing. The database consists of monophonic MIDI files which are modeled into strings, and the user sung query is modeled as a set of regular expressions (regexp), with consideration of possible key transpositions and tempo variations to tolerate imperfectly sung queries. An approximate regexp matching algorithm is developed to calculate the similarity between a regexp and a string, using edit distance as the metrics. The algorithm supports user sung queries starting anywhere in the database song, not necessarily from the beginning. Using the proposed formal models and algorithms, the similarity between the user sung query and each song in the database can be evaluated and the top-10 most similar results will be reported. We designed the approximate regexp matching algorithm in such way that all terms of the regexp can execute concurrently, which perfectly fits the massive parallelism provided by FPGA. The FPGA implemented melody matching engine (MME) is a parameterized modular architecture that can be reconfigured to implement different regexps by simply updating their parameter registers, and can therefore avoid the time-consuming code re-synthesis. MME also includes an on-board DDR2 memory to store the database, so that they can be read in to calculate edit distances locally on the board. This way, each MME forms a self-contained system and multiple MMEs can be clustered to increase parallel processing power, with virtually no overhead. MME is evaluated using the query corpus of ThinkIT with 355 sung files and database of 5563 MIDI files. It achieves a top-10 hit rate of 90.7% and a runtime of 19.4 seconds, averaging 54.6 milliseconds for a single query. MME achieves significant speedup over software-based systems while providing the same level of flexibility. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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