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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 834 条记录，以下是321-330 订阅

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Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays 13

Analysis of the area-delay performance of hybrid nanoelectro...

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23rd acm international Conference of the Great Lakes symposium on VLSI, GLSVLSI 2013

作者： Wang, Qin Heittmann, Arne Noll, Tobias G. Department of Electrical Engineering and Computer Systems RWTH Aachen University Schinkelstr. 2 D-52062 Aachen Germany

ISBN: (纸本)9781450319027

In this paper, an area-delay metric (AT) of hybrid memristive/CMOS memory architectures is discussed. The proposed memory circuit can be used as a lookup table in field programmable gate arrays (FPGAs) and is modeled by a passive nanoelectronic crossbar comprising resistive switches (RS) as memory elements. In particular, resistive switches which are based on the electrochemical metallization effect (ECM) are assumed. At the periphery, CMOS circuits are included with provide appropriate voltage levels for robust read and write operations. The optimization of the CMOS periphery was done for a 40-nm CMOS technology, and especially in regard to the physical properties of ECM cells which allows for the derivation of a realistic AT metric for the memory core circuit. For different architectural choices, the evaluation of the AT metric shows, that the area overhead which is caused by the peripheral CMOS circuits significantly determines the total circuit area. Under almost all conditions the required silicon area per bit is far beyond 4F2 (F: lithographic resolution), but for particular conditions the effective area per bit is smaller than the area per bit which is required for a corresponding SRAM core circuit. © 2013 acm.

关键词： Metallizing

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Improving high level synthesis optimization opportunity through polyhedral transformations 13

Improving high level synthesis optimization opportunity thro...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Zuo, Wei Liang, Yun Li, Peng Rupnow, Kyle Chen, Deming Cong, Jason Center for Energy-Efficient Computing and Applications School of EECS Peking University China University of Illinois Urbana-Champaign IL United States Advanced Digital Science Center Singapore Singapore Computer Science Department University of California Los Angeles CA United States School of Information and Electronics Beijing Institute of Technology China

ISBN: (纸本)9781450318877

High level synthesis (HLS) is an important enabling technology for the adoption of hardware accelerator technologies. It promises the performance and energy efficiency of hardware designs with a lower barrier to entry in design expertise, and shorter design time. State-of-the-art high level synthesis now includes a wide variety of powerful optimizations that implement efficient hardware. These optimizations can implement some of the most important features generally performed in manual designs including parallel hardware units, pipelining of execution both within a hardware unit and between units, and fine-grained data communication. We may generally classify the optimizations as those that optimize hardware implementation within a code block (intra-block) and those that optimize communication and pipelining between code blocks (inter-block). However, both optimizations are in practice difficult to apply. Real-world applications contain data-dependent blocks of code and communicate through complex data access patterns. Existing high level synthesis tools cannot apply these powerful optimizations unless the code is inherently compatible, severely limiting the optimization opportunity. In this paper we present an integrated framework to model and enable both intra- and inter-block optimizations. This integrated technique substantially improves the opportunity to use the powerful HLS optimizations that implement parallelism, pipelining, and fine-grained communication. Our polyhedral model-based technique systematically defines a set of data access patterns, identifies effective data access patterns, and performs the loop transformations to enable the intra- and inter-block optimizations. Our framework automatically explores transformation options, performs code transformations, and inserts the appropriate HLS directives to implement the HLS optimizations. Furthermore, our framework can automatically generate the optimized communication blocks for fine-grained communica

关键词： field programmable gate arrays (FPGA)

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Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources 13

Pipeline template and scheduling algorithm for mapping multi...

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23rd acm international Conference of the Great Lakes symposium on VLSI, GLSVLSI 2013

作者： Dong, Yazhuo Zhan, Wu Ye, Xiqing Naval Academy of Armament No. 3 Wanshou Street Haidian area Beijing City 100036 China

ISBN: (纸本)9781450319027

There are large numbers of high-level algorithms consisting of multiple loop nests in image compression, pattern recognition and digital signal processing. FPGA provides a convenient and flexible solution to speed up these loop-intensive algorithms. However, FPGA reconfiguration which needs a long time is inevitable when switching between the loop nests. This paper presents a parameterized pipeline template to execute all the loop nests in sequence without FPGA reconfiguration. Five steps are designed to decide the parameters. Experiments show that the pipeline template can achieve a comparative execution cycles for a loop comparing with the special hardware structure. © 2013 Authors.

关键词： field programmable gate arrays (FPGA)

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A compact FPGA-based Montgomery multiplier over prime fields 13

A compact FPGA-based Montgomery multiplier over prime fields

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23rd acm international Conference of the Great Lakes symposium on VLSI, GLSVLSI 2013

作者： Morales-Sandoval, Miguel Díaz-Pérez, Arturo Laboratorio de Tecnologías de la Información CINVESTAV-Tamaulipas Ciudad Victoria 87130 Mexico

ISBN: (纸本)9781450319027

This work describes a compact FPGA hardware architecture for computing modular multiplications over GF(p) using the Montgomery method, suitable for public key cryptography for embedded or mobile systems. The multiplier is parameterizable, allowing to evaluate the hardware design for different prime fields using different radix of the form β = 2k. The design uses only three k x k multipliers and three 2k-bit adders. The hardware organization of the multiplier maximizes the use of the multipliers processing iteratively the multiplicand, multiplier and modulus. The parametric design allows to study area-performance trade offs, in order to meet system requirements such as available resources, throughput, and efficiency. The proposed multiplier achieves a 1024-bit modular multiplication in 15.63 μs using k = 32. Compared to the most compact FPGA implementation previously reported, our proposed design uses 79% less FPGA resources with better efficiency expressed as Mbps/Slice. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Heterogeneous 3-D stacking, can we have the best of both (Technology) worlds? 13

Heterogeneous 3-D stacking, can we have the best of both (Te...

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2013 acm international symposium on Physical Design, ISPD 2013

作者： Madden, Liam Xilinx Inc. 2100 Logic Drive San Jose CA 95124 United States

ISBN: (纸本)9781450318679

Since the advent of integrated circuit technology in 1958, the industry has focused primarily on monolithic integration. Unfortunately, due to physical and economic issues, the vast majority of high performance analog chips, high density memory chips, and high performance digital chips are each built on separate technologies. Therefore, in order to deliver optimum system performance, power and cost, it is desirable to integrate multiple different die, each using its own optimized technology, in a single package. This paper describes the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). The heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic solution. Mounted on a passive silicon interposer with through-silicon vias (TSVs), the heterogeneous IC stack comprises FPGA ICs with 13.1-Gb/s transceivers and dedicated analog ICs with 28-Gb/s transceivers. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware 13

A hardware-oriented dynamically adaptive disparity estimatio...

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23rd acm international Conference of the Great Lakes symposium on VLSI, GLSVLSI 2013

作者： Akin, Abdulkadir Baz, Ipek Atakan, Baris Boybat, Irem Schmid, Alexandre Leblebici, Yusuf STI EPFL 1015 Lausanne Switzerland EEE METU Ankara Turkey EE SU Istanbul Turkey

ISBN: (纸本)9781450319027

The computational complexity of disparity estimation algorithms and the need of large size and bandwidth for the external and internal memory make the real-time processing of disparity estimation challenging, especially for High Resolution (HR) images. This paper proposes a hardware-oriented adaptive window size disparity estimation (AWDE) algorithm and its real-time reconfigurable hardware implementation that targets HR video with high quality disparity results. The proposed algorithm is a hybrid solution involving the Sum of Absolute Differences and the Census cost computation methods to vote and select the best suitable disparity candidates. It utilizes a pixel intensity based refinement step to remove faulty disparity computations. The AWDE algorithm dynamically adapts the window size considering the local texture of the image to increase the disparity estimation quality. The proposed reconfigurable hardware of the AWDE algorithm enables handling 60 frames per second on Virtex-5 FPGA at a 1024x768 XGA video resolution for a 120 pixel disparity range. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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acm/sigda international symposium on field programmable gate arrays - FPGA: Foreword

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 2011年 iii页

作者： Wawrzynek, John Compton, Katherine UC Berkeley United States University of Wisconsin-Madison United States

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Accelerating 3D-FFT using Hard Embedded Blocks in FPGAs

Accelerating 3D-FFT using Hard Embedded Blocks in FPGAs

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26th international Conference on VLSI Design Held Concurrently with 12th international Conference on Embedded Systems Design

作者： Varma, B. Sharat Chandra Paul, Kolin Balakrishnan, M. Indian Inst Technol Delhi Dept Comp Sci & Engn New Delhi India

ISBN: (纸本)9780769548890

Three dimensional Fast Fourier Transform (3D-FFT) is popularly used in many scientific applications in various domains like image processing, bioinformatics and molecular dynamics. Typically 3D-FFT computation takes significant part of the execution time of these applications. In order to speedup these applications, it becomes necessary to accelerate 3D-FFT computation. 3D-FFT can be accelerated using field programmable gate Array (FPGA) based accelerators. But speedup always may not be possible as FPGAs run at slower clock frequency vis-avis processors and the resources available in an FPGA device might not be sufficient for the implementation of a sufficient number of copies of the processing elements to compensate for the loss of clock frequency. FPGAs with heterogeneous mix of coarse grained hard blocks along with programmable soft logic, can facilitate implementing a much larger number of processing elements and thus achieve much higher speedups. Modern FPGAs do consist of different heterogeneous hard embedded blocks (HEBs) like multipliers, DSP blocks and memory units. It is easy to predict that many more such hard blocks will be embedded into future FPGAs. The evaluation approach to identify and incorporate HEBs is complex as there are many parameters and constraints like area, granularity routing resources, etc. that need to be considered in an integrated manner to get an efficient implementation. In this paper we show acceleration of 3D-FFT using future fabrics incorporating HEBs. By using these fabrics we show speedups of upto 1900x for 2048 point FFT. We also present an evaluation methodology to design future FPGA fabrics incorporating accelerators as hard embedded blocks. This methodology will be useful for i selection of blocks to be embedded into the fabric and ii evaluating the performance gain that can be achieved by such an embedding.

关键词： clocks digital signal processing chips fast Fourier transforms field programmable gate arrays

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Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient Recovery

Embedded Reconfigurable Augmented DC-DC Boost Converter for ...

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26th international Conference on VLSI Design Held Concurrently with 12th international Conference on Embedded Systems Design

作者： Mishra, Neeraj Jha, Niraj Kapat, Santanu Patra, Amit Indian Inst Technol Dept Elect Engn Kharagpur 721302 W Bengal India

ISBN: (纸本)9780769548890

A DC-DC boost converter is widely used for power management applications. However, the right-half-plane zero effect still remains a bottleneck for fast transient recovery. This paper is intended to propose an embedded reconfigurable boost converter solution with ultra-fast transient recovery through near-lossless augmentation. This augmentation branch requires an extra synchronous phase in parallel, comprising a small inductor and a half-bridge switch cell. This branch is activated only during large-signal transient recovery. The original converter topology is restored for steady state operations, thereby improving the overall efficiency. A prototype augmented boost converter is tested, and the proposed controller is implemented using an FPGA device. The extra branch closely nullifies current and voltage overshoot/undershoots. It is also expected to have almost no impact on efficiency.

关键词： DC-DC power convertors field programmable gate arrays

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Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors (abstract only) 13

Hardware acceleration of TEA and XTEA algorithms on FPGA, GP...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Vivek Venugopal Devu Manikantan Shila United Technologies Research Center E Hartford CT USA

ISBN: (纸本)9781450318877

field programmable gate arrays (FPGA) are extensively used for rapid prototyping in embedded system applications. While hardware acceleration can be done via specialized processors like a Graphical Processing Unit (GPU), they can also be accomplished with FPGAs for more specialized scenarios. GPUs essentially consist of massively parallel cores and have high memory bandwidth; FPGAs, on the other hand, provide flexibility in terms of customizable I/O and computational resources. In this paper, we explore the usage of GPUs and FPGAs as cryptographic co-processors in streaming dataflow systems with huge rate of data inhalation. Two classic lightweight encryption algorithms, Tiny Encryption Algorithm (TEA) and Extended Tiny Encryption Algorithm (XTEA), are targeted for implementation on GPUs and FPGAs. The GPU implementations of TEA and XTEA in this study depict a maximum speedup of 13x over CPU based implementation. The pipelined FPGA implementation is able to realize a throughput of 6-9x more than the GPU for small plaintext sizes.

关键词： cryptography graphics processing units tiny encryption algorithm field programmable gate arrays parallel processing

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