检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

804 篇 会议
30 篇 期刊文献

馆藏范围

834 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

671 篇 工学
- 617 篇 计算机科学与技术...
- 358 篇 软件工程
- 275 篇 电子科学与技术（可...
- 203 篇 电气工程
- 114 篇 信息与通信工程
- 45 篇 控制科学与工程
- 42 篇 动力工程及工程热...
- 34 篇 机械工程
- 23 篇 生物工程
- 14 篇 仪器科学与技术
- 13 篇 建筑学
- 12 篇 土木工程
- 11 篇 冶金工程
- 10 篇 化学工程与技术
- 10 篇 生物医学工程（可授...
- 8 篇 材料科学与工程（可...
- 6 篇 光学工程
- 4 篇 农业工程
243 篇 理学
- 195 篇 数学
- 40 篇 物理学
- 24 篇 生物学
- 23 篇 统计学（可授理学、...
- 10 篇 系统科学
- 7 篇 化学
72 篇 管理学
- 61 篇 管理科学与工程(可...
- 40 篇 工商管理
- 12 篇 图书情报与档案管...
19 篇 经济学
- 19 篇 应用经济学
16 篇 法学
- 14 篇 社会学
4 篇 教育学
- 4 篇 教育学
4 篇 农学
2 篇 医学

主题

371 篇 field programmab...
265 篇 field programmab...
48 篇 signal processin...
48 篇 clocks
45 篇 modulation
45 篇 ofdm
45 篇 estimation
44 篇 filtration
30 篇 fpga
22 篇 hardware
17 篇 routing
14 篇 computer archite...
14 篇 switches
13 篇 table lookup
11 篇 logic arrays
9 篇 prototypes
9 篇 systolic arrays
9 篇 optimization
9 篇 field-programmab...
9 篇 high-level synth...

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 xilinx
4 篇 stanford univ st...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 university of ca...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 department of co...

作者

21 篇 cong jason
20 篇 rose jonathan
11 篇 betz vaughn
10 篇 hauck scott
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 zhang zhiru
9 篇 chen deming
8 篇 wilton steven j....
8 篇 schmit herman
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 anderson jason h...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
5 篇 so hayden kwok-h...
5 篇 dehon andre
5 篇 cheung peter y. ...

语言

826 篇 英文
8 篇 其他

检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 834 条记录，以下是331-340 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Indirect connection aware attraction for FPGA clustering (abstract only) 13

Indirect connection aware attraction for FPGA clustering (ab...

引用

proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Meng Yang Jiarong Tong A.E.A. Almaini State Key Lab of ASIC Fudan University Shanghai China Edinburgh Napier University Edinburgh United Kingdom

ISBN: (纸本)9781450318877

Indirect connection aware attraction clustering algorithm is proposed for clustered field programmable gate array architecture model to achieve simultaneously optimization of several performance metrics. A new cost function considers the attraction of the subsequent basic logic elements (BLEs) to the selected cluster, the number of the used pins already in the cluster, as well as critical path delay. The attractions of which BLEs are directly and indirectly connected to the selected cluster are taken into account. As a result, more external nets are absorbed into clusters, less number of pins per cluster and fewer clusters are required. Hence, smaller channel width is required for routing and speed of the design is improved. Performance comparisons are carried out in details with respect to state-of-the-art clustering techniques interconnect resource aware clustering (iRAC) and many-objective clustering (MO-Pack). Results show that the proposed algorithm outperforms these two clustering approaches with achievements of 38.8% and 42.2% respectively in terms of channel widths and 40.1% and 44.8% respectively in terms of number of external nets but with no critical path and area overhead.

关键词： FPGAs computer aided design clustering optimization field-programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

FPGA-based HPC application design for non-experts (abstract only) 13

FPGA-based HPC application design for non-experts (abstract ...

引用

proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： David Uliana Krzysztof Kepa Peter Athanas Virginia Tech Blacksburg VA USA

ISBN: (纸本)9781450318877

This paper presents bFlow, an FPGA development framework for the rapid prototyping and implementation of hardware accelerators for hybrid computing platforms. This framework makes use of an abstracted, graphical front-end usable by those without computer engineering backgrounds, as well as an accelerated back-end that speeds up compilation times, increasing turns-per-day. bFlow's performance, usability, and application to the acceleration of big-data life-science problems verified by participants of the NSF-funded Summer Institute organised by the Virginia Bioinformatics Institute (VBI). In less than two weeks, a group of four non-computer science/computer engineering participants made modifications to a reference Smith-Waterman implementation, adding functionality and scaling throughput by a factor of four to 600 million base pairs per second.

关键词： field-programmable gate arrays bioinformatics co-processor heterogeneous computing design productivity convey HC-1 big-data

来源：评论

学校读者我要写书评

暂无评论

QuickRec: Prototyping an intel architecture extension for record and replay of multithreaded programs 13

QuickRec: Prototyping an intel architecture extension for re...

引用

40th Annual international symposium on Computer Architecture, ISCA 2013

作者： Pokam, Gilles Danne, Klaus Pereira, Cristiano Kassa, Rolf Kranich, Tim Hu, Shiliang Gottschlich, Justin Honarmand, Nima Dautenhahn, Nathan King, Samuel T. Torrellas, Josep Intel Corporation United States University of Illinois Urbana-Champaign United States

ISBN: (纸本)9781450320795

There has been significant interest in hardware-assisted deterministic Record and Replay (RnR) systems for multithreaded programs on multiprocessors. However, no proposal has implemented this technique in a hardware prototype with full operating system support. Such an implementation is needed to assess RnR practicality. This paper presents QuickRec, the first multicore Intel Architecture (IA) prototype of RnR for multithreaded programs. QuickRec is based on QuickIA, an Intel emulation platform for rapid prototyping of new IA extensions. QuickRec is composed of a Xeon server platform with FPGA-emulated second-generation Pentium cores, and Capo 3, a full software stack for managing the recording hardware from within a modified Linux kernel. This paper's focus is understanding and evaluating the implementation issues of RnR on a real platform. Our effort leads to some lessons learned, as well as to some pointers for future research. We demonstrate that RnR can be implemented efficiently on a real multicore IA system. In particular, we show that the rate of memory log generation is insignificant, and that the recording hardware has negligible performance overhead. However, the software stack incurs an average recording overhead of nearly 13%, which must be reduced to enable always-on use of RnR. Copyright 2013 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Are FPGAs suffering from the innovator's dilemna? 13

Are FPGAs suffering from the innovator's dilemna?

引用

proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Vaughn Betz Jason Cong University of Toronto Toronto ON Canada UCLA Los Angeles CA USA

ISBN: (纸本)9781450318877

FPGAs constitute a highly profitable industry, with approximately $5 billion of sales per year. High barriers to entry keep most companies away, and enable high profit margins for the incumbents. The industry has grown greatly over the years, but still constitutes a small portion of the overall semiconductor market. This raises the question to be addressed by this panel: is the FPGA community innovating as much as it should, or is a bias to maintain high profit margins and protect the cash flow of the current FPGA market holding us back from exploring new ideas and products that could greatly expand the appeal of and market for FPGA-related technology? This would be a classic case of the innovator's dilemma defined by Clayton Christensen: it is difficult for a company to engage in creative destruction of a cash cow *** distinguished panel of experts will discuss whether we are seeing major innovation in architectures, design flows and applications, or only incremental improvements. We will also discuss if any new (possibly low margin) application domain is left out by the FPGA industry, what radical ideas should be explored, and whether large incumbents, new startups, academia or some combination are best able to attack these new areas.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only) 13

Hybrid masking using intra-masking dual-rail memory on LUT f...

引用

proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Anh-Tuan Hoang Takeshi Fujino Ritsumeikan University Shiga prefecture Kusatsu city Japan

ISBN: (纸本)9781450318877

In current countermeasure design trends against Different Power Analysis (DPA), security at gate level is required in addition to the security algorithm. Several Dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate Array (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This paper describes our novel Hybrid Masking implementations using Intra-Masking Dual-rail Memory (IMDRM) approach for Side-channel-resistant AES. The hybrid masking scheme includes an additive mask and a multiplicative mask. The additive masking scheme utilizes a dual-rail memory, in which all unsafe nodes, such as unmasking and masking, the dual-rail memory and buses are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. The multiplicative masking scheme is then applied over the additive masked values. It removes the joint-leakage, which is caused by the joint processing of the masks and the masked values inside the dual-rail memory. The design is independent of the cryptographic algorithm and persistent with SCA attacks even after 1,000,000 traces. It also occupied smaller hardware size than most other advanced SCA resistant implementations such as the Wave Dynamic Differential Logic, the Masked Dual-Rail Pre-charge Logic, and the Intra-Masking Dual-Rail Memory.

关键词： SCA resistance differential power analysis (DPA) side-channel attack masking intra-masking dual-rail memory on LUT dual-rail memory field programmable gate array (FPGA) hybrid masking AES

来源：评论

学校读者我要写书评

暂无评论

Defect recovery in nanodevice-based programmable interconnects (abstract only) 13

Defect recovery in nanodevice-based programmable interconnec...

引用

proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Jason Cong Bingjun Xiao UCLA Los Angeles CA USA

ISBN: (纸本)9781450318877

This work focuses on defect tolerance for nanodevice-based programmable interconnects of FPGAs. A single nanodevice can function as a routing switch in place of a pass transistor and its six-transistor SRAM cell in conventional FPGAs. Defects of nanodevices in programmable interconnects are manifested as losses of configurability and can be categorized into stuck- open defect and stuck- closed defect. First, we show that the stuck-closed defects of nanodevices have a much higher impact than the stuck-open defects. Instead of simply avoiding the stuck-closed defects, we recover them by treating them as shorting constraints in the routing. We develop a scalable algorithm to perform timing-driven routing under these extra constraints. We extend the idea of the resource negotiation to balance the goals of timing and routability under shorting constraints. We also develop several techniques to guide the router to map the shorting clusters to those nets with more shared paths for better utilization of routing resources while automatically balancing it with circuit performance. We also enhance the placement algorithm to recover logic blocks which become virtually unusable due to shorted pins. Simulation results show that at the up-to-date level of nanodevice defects (108-1011x higher than CMOS), compared to the simple avoidance method, our approach reduces the degradation of resource usage by 87%, improves the routability by 37%, and reduce the degradation of circuit performance by 36%, at a negligible overhead of tool runtime.

关键词： nanodevice defect tolerance route programmable interconnects placement

来源：评论

学校读者我要写书评

暂无评论

A Fast Discrete Placement Algorithm for FPGAs 12

A Fast Discrete Placement Algorithm for FPGAs

引用

20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Wu, Qinghong McElvain, Kenneth S. Synopsys Inc Mountain View CA 94043 USA

ISBN: (纸本)9781450311557

Good FPGA placement is crucial to obtain the best Quality of Results (QoR) from FPGA hardware. Although many published global placement techniques place objects in a continuous ASIC-like environment, FPGAs are discrete in nature, and a continuous algorithm cannot always achieve superior QoR by itself. Therefore, discrete FPGA-specific detail placement algorithms are used to improve the global placement results. Unfortunately, most of these detail placement algorithms do not have a global view. This paper presents a discrete "middle" placer that fills the gap between the two placement steps. It works like simulated annealing, but leverages various acceleration techniques. It does not pay the runtime penalty typical of simulated annealing solutions. Experiments show that with this placer, final QoR is significantly better than with the global-detail placer approach.

关键词： Computer-aided design (CAD) individual cell temperature window masking dynamic window field-programmable gate array (FPGA) placement simulated annealing

来源：评论

学校读者我要写书评

暂无评论

Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in FPGAs 12

Reducing the Cost of Floating-Point Mantissa Alignment and N...

引用

20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Moctar, Yehdhih Ould Mohammed George, Nithin Parandeh-Afshar, Hadi Ienne, Paolo Lemieux, Guy G. F. Brisk, Philip Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781450311557

In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemented using several rows of small multiplexers;unfortunately, multiplexer-based logic structures map poorly onto LUTs. FPGAs, meanwhile, contain a large number of multiplexers in the programmable routing network;these multiplexer are placed under static control of the FPGA's configuration bitstream. In this work, we modify some of the routing multiplexers in the intra-cluster routing network of a CLB in an FPGA to implement shifters for floating-point mantissa alignment and normalization;the number of CLBs required for these operations is reduced by 67%. If shifting is not required, the routing multiplexers that have been modified can be configured to operate as normal routing multiplexers, so no functionality is sacrificed. The area overhead incurred by these modifications is small, and there is no need to modify every routing multiplexer in the FPGA. Experiments show that there is no negative impact in terms of clock frequency or routability for benchmarks that do not use the dynamic multiplexers.

关键词： field programmable gate Array (FPGA) Floating-point Mantissa Alignment Normalization

来源：评论

学校读者我要写书评

暂无评论

Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper-Resistant AES on FPGA 12

Intra-Masking Dual-Rail Memory on LUT Implementation for Tam...

引用

20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Hoang, Anh-Tuan Fujino, Takeshi Ritsumeikan Univ Kusatsu Shiga 5258577 Japan

ISBN: (纸本)9781450311557

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This paper describes our novel masked dual-rail pre-charged memory approach, called "intra-masking dual-rail memory on LUT," and its implementation on FPGA for tamper-resistant AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and the dual-rail memory and buses are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. The design is independent of the cryptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on FPGA showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced tamper-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.

关键词： Side-Channel Attack Differential Power Analysis (DPA) Masking Dual-Rail Memory Intra-Masking Dual-Rail Memory on LUT Tamper Resistance AES field programmable gate Array (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Leveraging latency-insensitivity to ease multiple FPGA design 12

Leveraging latency-insensitivity to ease multiple FPGA desig...

引用

2012 acm/sigda international symposium on field programmable gate arrays, FPGA'12

作者： Fleming, Kermin Elliott Adler, Michael Pellauer, Michael Parashar, Angshuman Mithal, Arvind Emer, Joel Intel Corporation VSSAD Group Hudson MA United States Massachusetts Institute of Technology Computer Science and A.I. Laboratory Cambridge MA United States

ISBN: (纸本)9781450311557

Traditionally, hardware designs partitioned across multiple FPGAs have had low performance due to the inefficiency of maintaining cycle-by-cycle timing among discrete FPGAs. In this paper, we present a mechanism by which complex designs may be efficiently and automatically partitioned among multiple FPGAs using explicitly programmed latency-insensitive links. We describe the automatic synthesis of an area efficient, high performance network for routing these inter-FPGA links. By mapping a diverse set of large research prototypes onto a multiple FPGA platform, we demonstrate that our tool obtains significant gains in design feasibility, compilation time, and even wall-clock performance. © 2012 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共84页 << < 30 31 32 33 34 35 36 37 38 39 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：