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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 834 条记录，以下是361-370 订阅

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A 65nm Flash-Based FPGA Fabric Optimized for Low Cost and Power 11

A 65nm Flash-Based FPGA Fabric Optimized for Low Cost and Po...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Greene, Jonathan Kaptanoglu, Sinan Feng, Wenyi Hecht, Volker Landry, Joel Li, Fei Krouglyanskiy, Anton Morosan, Mihai Pevzner, Val Microsemi Corp SOC Prod Grp Mountain View CA 94043 USA

ISBN: (纸本)9781450305549

This paper describes a non-volatile reprogrammable FPGA fabric, whose configuration data are provided directly by flash memory. The fabric is optimized for low-cost, low-power applications, leveraging the density of flash and the elimination of conventional configuration SRAM and its attendant static power. After surveying the necessary background on flash and its application to FPGAs, the IT flash cell is described along with relevant novel aspects of the fabric architecture. The addition of a third level of switching between inter-cluster signals and logic inputs helps to reduce area and raise typical utilization above 95%. Despite the longer signal path, performance is maintained by synergism between the improved routing flexibility and extreme minimization of the fastest LUT input delay. Test cost is reduced by built-in circuits that can test all switches without reprogramming the flash memory. The fabric has been implemented in a 65nm CMOS embedded flash process.

关键词： FPGA architecture flash memory Clos network built-in self-test programmable routing input interconnection block IIB packing

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Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect 11

Architecture description and packing for logic blocks with h...

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Luu, Jason Anderson, Jason Helge Rose, Jonathan Scott Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450305549

The development of future FPGA fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it. In this paper, we present a new logic block description language that can depict complex intra-block interconnect, hierarchy and modes of operation. These features are necessary to support modern and future FPGA complex soft logic blocks, memory and hard blocks. The key part of the CAD flow associated with this complexity is the packer, which takes the logical atomic pieces of the complex blocks and groups them into whole physical entities. We present an area-driven generic packing tool that can pack the logical atoms into any heterogeneous FPGA described in the new language, including many different kinds of soft and hard logic blocks. We gauge its area quality by comparing the results achieved with a lower bound on the number of blocks required, and then illustrate its explorative capability in two ways: on fracturable LUT soft logic architectures, and on hard block memory architectures. The new infrastructure attaches to a flow that begins with a Verilog front-end, permitting the use of benchmarks that are significantly larger than the usual ones, and can target heterogenous FPGAs. Copyright 2011 acm.

关键词： field programmable gate arrays (FPGA)

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Accelerating Itoh-Tsujii multiplicative inversion algorithm for FPGAs 11

Accelerating Itoh-Tsujii multiplicative inversion algorithm ...

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proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

作者： Roy, Sujoy Sinha Rebeiro, Chester Mukhopadhyay, Debdeep Department of Computer Science and Engineering Indian Institute of Technology Kharagpur West Bengal-721302 India

ISBN: (纸本)9781450306676

The Itoh-Tsujii multiplicative inversion algorithm (ITA) is the most efficient finite field inversion algorithm for hardware based implementations over extended binary fields. In this paper we propose a novel technique to reduce the computation time of the ITA by saving clock cycles without increasing the delay and area significantly. In order to compare, we have designed the architecture for the ITA in the field GF(2193). The architecture uses a configuration of a cascaded quad-root block in parallel with a 297 circuit to compute the inverse in only .53 μsecs on a Virtex E FPGA and .14 μsecs on a Virtex V FPGA. Experimental results are presented to support that the architecture takes least computation time compared to other reported results. Copyright © 2011 by ASME.

关键词： field programmable gate arrays (FPGA)

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Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology 11

Congestion and track usage improvement of large FPGAs using ...

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proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

作者： Alipour, Mehdi Seyed Javadi, M.H. Jahanian, Ali Qazvin Islamic Azad Univ. Iran Shahid Beheshti Univ. Iran

ISBN: (纸本)9781450306676

Asynchronous serial transceivers have been recently used for data multiplexing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the serial transmission but these links have not been exploited in FPGAs yet. In this paper, we present a new architecture corresponding with a routing algorithm to use the asynchronous wire multiplexing technique in FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (9.37% and 9.03%, respectively) by using the asynchronous wire multiplexing without any performance degradation in cost of a little overhead in area and computation time (2% and 0.84%, respectively). Copyright © 2011 by ASME.

关键词： field programmable gate arrays (FPGA)

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mrFPGA: A novel FPGA architecture with memristor-based reconfiguration 11

mrFPGA: A novel FPGA architecture with memristor-based recon...

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proceedings of the 2011 IEEE/acm international symposium on Nanoscale Architectures

作者： Cong, Jason Xiao, Bingjun Department of Computer Science University of California Los Angeles CA United States

ISBN: (纸本)9781457709944

In this paper, we introduce a novel FPGA architecture with memristor-based reconfiguration (mrFPGA). The proposed architecture is based on the existing CMOS-compatible memristor fabrication process. The programmable interconnects of mrFPGA use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay but without using a 3D die-stacking process. Using memristors to build up the interconnects can also provide capacitance shielding from unused routing paths and reduce interconnect delay further. Moreover we propose an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup. Compared to the fixed buffer pattern in conventional FPGAs, the positions of inserted buffers in mrFPGA are optimized on demand. A complete CAD flow is provided for mrFPGA, with an advanced P&R tool named mrVPR that was developed for mrFPGA. The tool can deal with the novel routing structure of mrFPGA, the memristor shielding effect, and the algorithm for optimal buffer insertion. We evaluate the area, performance and power consumption of mrFPGA based on the 20 largest MCNC benchmark circuits. Results show that mrFPGA achieves 5.18x area savings, 2.28x speedup and 1.63x power savings. Further improvement is expected with combination of 3D technologies and mrFPGA. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Evaluation of FPGA routing architectures under process variation 11

Evaluation of FPGA routing architectures under process varia...

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proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

作者： Pourhashemi, Fatemeh Sadat Saheb Zamani, Morteza Amirkabir University of Technology Tehran Iran

ISBN: (纸本)9781450306676

Uncertainty in performance of FPGAs is becoming an important issue due to increased process variations in nanometer regime. Therefore, it is vital to decrease the impact of variability in these devices. FPGA routing architecture enhancement can be an effective way, because as feature size scales down, routing delay dominates logic circuit delay. In this paper, unidirectional and bidirectional routing architectures are compared. We show that bidirectional architecture is better in terms of robustness against variation when short wire segments are considered. However as wire length increases, unidirectional routing architecture would be the preferred option. Experimental results show that in unidirectional routing architecture towards bidirectional for wire length of 8, it has obtained 36% and 20% improvement in standard deviation and 3μ+σ of circuit delay, respectively. Copyright © 2011 by ASME.

关键词： field programmable gate arrays (FPGA)

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Power estimation of dividers implemented in FPGAs 11

Power estimation of dividers implemented in FPGAs

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proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

作者： Jevtic, Ruzica Jovanovic, Bojan Carreras, Carlos Dept. of Electronics Engineering ETSIT Technical University of Madrid Madrid 28040 Spain Dept. of Electronics Faculty of Electronics Engineering University of Nis Nis 18000 Serbia

ISBN: (纸本)9781450306676

We present a methodology for power estimation of non-fractional divider cores implemented in FPGAs. The methodology takes into account the divider structure and the signal statistics at the inputs: mean, variance, and autocorrelation. An analytical model is used for switching activity computation. The strong data dependency observed at the inputs of the divider basic elements is properly modelled in order to improve the model accuracy. The methodology is capable of obtaining fast and accurate estimates when compared to both, real on-board measurements and XPower. The mean relative error is less than 10%, with a maximum error of 22% when estimates are compared to on-board measurements and less than 11% when estimates are compared to low-level estimates provided by the commercial tool. Copyright © 2011 by ASME.

关键词： field programmable gate arrays (FPGA)

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proceedings of the 7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

Proceedings of the 7th ACM SIGDA International Symposium on ...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

ISBN: (纸本)9781605584102

The proceedings contain 34 papers. The topics discussed include: emerging application domains - research challenges and opportunities for FPGAs;towards automated ECOs in FPGAs;clock power reduction for Virtex-5 FPGAs;choose-your-own-adventure routing: lightweight load-time defect avoidance;towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs;a comparison of via-programmable gate array logic cell circuits;a comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation;a high-performance FPGA architecture for restricted Boltzmann machines;FPGA-based front-end electronics for positron emission tomography;FPGA-based face detection system using Haar classifiers;a 17ps time-to-digital converter implemented in 65nm FPGA technology;and FPGA technology mapping with encoded libraries and staged priority cuts.

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A statistical power estimation methodology embedded in a SystemC code translator 11

A statistical power estimation methodology embedded in a Sys...

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24th symposium on Integrated Circuits and Systems Design, SBCCI2011

作者： Kuehnle, Matthias Wagner, Andre Becker, Juergen Karlsruhe Institute of Technology Karlsruhe Germany

ISBN: (纸本)9781450308281

This work describes a methodology for estimating switching activity, which is needed to evaluate power dissipation. The methodology is integrated in a VHDL to SystemC translation process and therefore needs no additional source modifications by the user. The SystemC model is favoured to allow a homogeneous system simulation environment, which speeds up the simulation. The translation process further implements an approach to wrap RTL to transaction level interfaces so that the translated module can be connected to a system level simulator. The switching analysis is based on a statistical model of the underlying HW structure and a preceding analysis of the input dataset. The accuracy and speed-up of the approach is finally illustrated and compared to conventional steps of a power analysis flow. © 2011 acm.

关键词： field programmable gate arrays (FPGA)

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Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA

Energy minimum operation in a reconfigurable gate-level pipe...

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IEEE/acm international symposium on Low-Power Electronics and Design

作者： Devlin, Benjamin Ikeda, Makoto Asada, Kunihiro Dept. of Electronic Engineering University of Tokyo Japan University of Tokyo Japan

ISBN: (纸本)9781612846590

A 65nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signalling allows the FPGA to operate at voltages down to 370mV without any parameter tuning. We show both 2.6x total energy reduction and 6.4x performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8x improvement in power-delay product (PDP) and 2 x performance improvement. When compared to a synchronous FPGA in a similar process we are able to show up to 84.6x PDP improvement. We also show energy minimum operation for maximum throughput on the power gated SSFPGA is achieved at 0.6V, 27fJ/operation at 264MHz. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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