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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 834 条记录，以下是421-430 订阅

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Improved placement for hierarchical FPGAs exploiting local interconnect resources 09

Improved placement for hierarchical FPGAs exploiting local i...

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22nd symposium on Integrated Circuits and Systems Design, SBCCI 2009

作者： Matrose, Valerij Gremzow, Carsten Berlin University of Technology Faculty of Computer Engineering and Microelectronics Franklinstrasse 28/29 Berlin Germany

ISBN: (纸本)9781605587059

The majority of networks subject to routing in almost every FPGA design consist of networks with only 2 to 4 terminals. These usually connect to directly adjacent logic cells. In order to make best use of this circumstance commercial FPGA architecture vendors provide dedicated local routing resources on the inter and intra logic block level. Previous routability-driven placement algorithms try to minimize utilization of global routing resources without taking local routing resources into account. This paper presents a new placement algorithm MPCPlace (Multipass Clustering and Placement) which makes specific use of local routing resources and hence reduces congestion on global routing resources and greatly improves overall routability in FPGA designs. The results obtained with the new placement algorithm will be compared to the SCPlace-Algorithm as well as the commercial Altera Quartus II software for various real world designs. The benchmark results at hand indicate for the new MPCPlace algorithm an average increase in routing resource utilization of up to 12.5% as well as a peak improvement of 10%. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Parameterizable floating-point library for arithmetic operations in FPGAs 09

Parameterizable floating-point library for arithmetic operat...

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22nd symposium on Integrated Circuits and Systems Design, SBCCI 2009

作者： Sánchez, Diego F. Muñoz, Daniel M. Llanos, Carlos H. Ayala-Rincón, Mauricio Pós-Graduação em Sistemas Mecatrônicos Engenharia Mecânica Universidade de Brasília 70910-900 Brasília D.F. Brazil Instituto de Ciências Exatas Universidade de Brasília 70910-900 Brasília D.F. Brazil

ISBN: (纸本)9781605587059

Floating-point operations are an essential requisite in a wide range of computational and engineering applications that need good performance and high precision. Current advances in VLSI technology raised the density integration fast enough, allowing the designers to develop directly in hardware several floating-point operations commonly implemented in software. Until now, most of the research has not focused on the tradeoff among the need of high performance and the cost of the size of logic area, associated with the level of precision, parameters that are very important in a wide variety of applications such as robotics, image and digital signal processing. This paper describes an FPGA implementation of a parameterizable floating-point library for addition/subtraction, multiplication, division and square root operations. Architectures based on Goldschmidt algorithm were implemented for computing floating-point division and square root. The library is parameterizable by bit-width and number of iterations. An analysis of the mean square error and the cost in area consumption is done in order to find, for general purpose applications, the feasible bit-width representation, number of iterations and number of addressable words for storing initial seeds of the Goldschmidt algorithm. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Emerging application domains: research challenges and opportunities for FPGAs 09

Emerging application domains: research challenges and opport...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Jason H. Anderson University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

Communications infrastructure, data processing and industrial electronics are the cornerstone application areas for programmable logic today. But what are the application domains of tomorrow? What nascent application areas could explode the growth of programmable logic usage and expand the programmable market? In this workshop, we will hear speakers from industry and academia talk about the emerging application areas for FPGAs and the challenges and opportunities in these areas. We will consider how programmable hardware and the associated tools should be enhanced to become better-suited to tomorrow's applications. The overarching aim of the workshop is to seed ideas in the research community by giving an applications perspective of the fertile topics for future research on FPGA architecture, CAD and applications.

关键词： high-performance computing field-programmable gate array applications performance power fpga reconfigurable computing

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Towards a hardware fault-injection testbed to support reproducible resiliency experiments

Towards a hardware fault-injection testbed to support reprod...

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2009 Workshop on Resiliency in High Performance, Resilience'09, Co-located with the 2009 international symposium on High Performance Distributed Computing Conference, HPDC'09

作者： Sass, Ron Sharma, Rahul R. DeBardeleben, Nathan Reconfigurable Computing Systems Lab. Univ. of N. Carolina at Charlotte 9201 University City Blvd. Charlotte NC 28223 United States Los Alamos National Laboratory MS B272 P. O. Box 1663 Los Alamos NM 87544 United States

ISBN: (纸本)9781605585932

As the largest computers in world continue to scale up to very large number of nodes, significant new problems emerge. Due to a number of different sources, hard and soft failures cause correctness issues and performance degradation in high component count machines. These issues simply do not occur at an appreciable rate in smaller scale machines. This presents a serious problem to researchers interested in studying and countering the issues because effects are not reproducible smaller scale testbeds. The Reconfigurable Computing Cluster (RCC) project is investigating the feasibility of using just FPGAs accelerators to build a high end computing computing system. However, since the hardware is very configurable, it is possible to also use this infrastructure to introduce special-purpose hardware cores that are designed to perturb or corrupt an existing system in a controlled way. This architecture offers an ideal platform for performing fault injections and "Heisenberg-free" monitoring of parallel programs. This work-in-progress describes several potential fault injectors and system monitors. A "bus cycle stealer" is demonstrated. This small hardware core can be programmed to wake up periodically and execute a variable number bus transactions. The effect on performance (single node and 16 node systems) are reported. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Architectural Improvements for field programmable Counter arrays: Enabling Efficient Synthesis of Fast Compressor Trees on FPGAs 08

Architectural Improvements for Field Programmable Counter Ar...

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16th acm/sigda international symposium on field-programmable gate arrays

作者： Cevrero, Alessandro Athanasopoulos, Panagiotis Parandeh-Afshar, Hadi Verma, Ajay K. Brisk, Philip Gurkaynak, Frank K. Leblebici, Yusuf Ienne, Paolo Ecole Polytech Fed Lausanne Inst Microelect & Microsyst Microelect Syst Lab CH-1015 Lausanne Switzerland

ISBN: (纸本)9781595939340

The field programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addition and multiplication operations into large multi-input addition operations, which are synthesized as compressor trees on the FPCA;the remaining portion of the circuit is synthesized on the FPGA. This paper presents a series of architectural improvements to the FPCA that reduce routing delay, increase flexibility and component utilization, and simplify the integration process. Using an FPGA containing six FPCAs, we observed average and maximum speedups of 1.60x and 2.40x on a set of arithmetic benchmarks.

关键词： FPGA field programmable Counter Array (FPCA)

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Architecture-Specific Packing for Virtex-5 FPGAs 08

Architecture-Specific Packing for Virtex-5 FPGAs

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16th acm/sigda international symposium on field-programmable gate arrays

作者： Ahmed, Taneem Kundarewich, Paul D. Anderson, Jason H. Taylor, Brad L. Aggarwal, Rajat Xilinx Inc Toronto ON Canada

ISBN: (纸本)9781595939340

We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA - the Xilinx (R) Virtex (TM) -5 FPGA. Two aspects of packing are discussed: 1) packing for general logic blocks, and 2) packing for large IP blocks. Virtex-5 logic blocks contain dual-output 6-input look-up-tables (LUTs). Such LUTs call implement any single logic function requiring no more than 6 inputs, or any two logic functions requiring no more than 5 distinct inputs. The second LUT Output is associated with slower speed, and therefore, must be used judiciously. We present placement-based techniques for dual-output LUT packing that;lead to improved area-efficiency and power, with minimal performance degradation. We then move on to address packing for large IP blocks, specifically, block RAMs and DSPs. We present a packing optimization that is widely applicable in DSP designs that leads to significantly improved design performance.

关键词： field-programmable gate arrays FPGAs optimization packing placement power performance

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A novel FPGA logic block for improved arithmetic performance 08

A novel FPGA logic block for improved arithmetic performance

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16th acm/sigda international symposium on field-programmable gate arrays, FPGA 2008

作者： Parandeh-Afshar, Hadi Brisk, Philip Ienne, Paolo School of Computer and Communication Sciences CH-1015 Lausanne Switzerland

ISBN: (纸本)9781595939340

To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional fast carry-chains that concatenate adjacent compressors and can be routed locally without the global routing network. Unlike previous carry-chains for binary and ternary addition, the carry chain used by the new cell only spans 2 logic blocks, which significantly improves the delay of multi-input addition operations mapped onto the FPGA. The delay and area overhead that arises from augmenting a traditional FPGA logic cell with the new compressor structure is minimal. Using this new cell, we observed an average speedup in combinational delay of 1.41 compared to adder trees synthesized using ternary adders. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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TORCH: A design tool for routing channel segmentation in FPGAs 08

TORCH: A design tool for routing channel segmentation in FPG...

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16th acm/sigda international symposium on field-programmable gate arrays, FPGA 2008

作者： Lin, Mingjie Gamal, Abbas El Department of Electrical Engineering Stanford University CA 94305 United States

ISBN: (纸本)9781595939340

A design tool for routing channel segmentation in island-style FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing channel segmentation using the average interconnect power-delay product as a performance metric, which is estimated from placed and routed designs. A simulated- annealing procedure is used, whereby segmentation is incrementally changed in each iteration, the benchmark designs are mapped using VPR, and the performance metric is computed to decide whether to accept or reject the new segmentation. Run time is signi cantly reduced by using incremental routing in each iteration and parallelizing the metric evaluation. Experimental results using the MCNC benchmark designs demonstrate an average of 22% and 15% reduction in delay and power relative to a baseline segmentation. The results also show that average segment length should decrease with technology scaling. Finally, we demonstrate how the tool can be used to optimize other aspects of programmable routing in an FPGA. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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A hardware framework for the fast generation of multiple ong-period random number streams

A hardware framework for the fast generation of multiple ong...

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16th acm/sigda international symposium on field-programmable gate arrays, FPGA 2008

作者： Dalal, Ishaan L. Stefan, Deian Dept. of Electrical Engineering Cooper Union New York NY 10003 United States

ISBN: (纸本)9781595939340

Stochastic simulations and other scientific applications that depend on random numbers are increasingly implemented in a parallelized manner in programmable logic. High-quality pseudo-random number generators (PRNG), such as the Mersenne Twister, are often based on binary linear recurrences and have extremely long periods (more than 21024). Many software implementations of such PRNGs exist, but hardware implementations are rare. We have developed an optimized, resource-efficient parallel framework for this class of random number generators that exploits the underlying algorithm as well as FPGA-specific architectural features. The framework also incorporates fast "jump-ahead" capability for these PRNGs, allowing simultaneous, independent sub-streams to be generated in parallel by partitioning one long-period pseudorandom sequence. We demonstrate parallelized implementations of three types of PRNGs - the 32-, 64- and 128-bit SIMD Mersenne Twister - on Xilinx Virtex-II Pro FPGAs. Their area/throughput performance is impressive: for example, compared clock-for-clock with a previous FPGA implementation, a "two-parallelized" 32-bit Mersenne Twister uses 41% fewer resources. It can also scale to 350 MHz for a throughput of 22.4 Gbps, which is 5.5x faster than the older FPGA implementation and 7.1x faster than a dedicated software implementation. The quality of generated random numbers is verified with the standard statistical test batteries diehard and TestU01. We also present two real-world application studies with multiple RNG streams: the Ziggurat method for generating normal random variables and a Monte Carlo photon-transport simulation. The availability of fast long-period random number generators with multiple streams accelerates hardware-based scientific simulations and allows them to scale to greater complexities. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Placement Challenges for Structured ASICs 08

Placement Challenges for Structured ASICs

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acm international symposium on Physical Design

作者： Schmit, Herman Gupta, Amit Ciobanu, Radu eEASIC Corp 2585 Augustine Ave Santa Clara CA 95054 USA Easic Corp Iasi Romania

ISBN: (纸本)9781605580487

The placement problem for structured ASICs combines aspects of the standard cell ASIC placement problem and FPGA placement. Similarities with ASIC placement include the number and size of the place-able objects and the need to consider buffering within placement. Similarities with FPGA placement include the existence of discrete legal locations for all types of objects, the constraints caused by "intrinsic" connections, such as clock, reset or 10 signals and fixed routing tracks. The research community has provided detailed analysis of various different solutions for the standard cell placement problem over the last two decades. FPGA placement research has not focused on the legalization issues. Architecturally, FPGAs are changing to focus more on synthesis and clustering than fine-grained placement to meet timing. In this paper we discuss the similarities and differences between FPGA, Standard Cell, and Structured ASIC placement, and we present new representations and tests cases for the structured ASIC problem.

关键词： field programmable gate arrays Placement Structured ASICs

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