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FPGA-based hardware/software Co-design for chirplet signal decomposition 08

FPGA-based hardware/software Co-design for chirplet signal d...

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GLSVLSI 2008: 18th acm Great Lakes symposium on VLSI 2008

作者： Lu, Yufeng Oruklu, Erdal Saniie, Jafar Electrical and Computer Engineering Bradley University Peoria IL 61625 United States Electrical and Computer Engineering Illinois Institute of Technology Chicago IL 60613 United States

ISBN: (纸本)9781595939999

In various signal processing applications, decomposition and analysis of non-stationary signals is a challenging problem. In this work, we present a computationally efficient method, fast chirplet signal decomposition (FCSD) algorithm, for decomposing highly convoluted signals into a linear expansion of chirplets, and successively estimates the chirplet parameters. These parameters are capable of representing a broad range of echo shapes, including the broad-band, narrow-band, symmetric, skewed, nondispersive or dispersive, and have significant physical interpretations for radar, sonar, and ultrasonic imaging applications. For the real-time implementation of chirplet signal decomposition algorithm, an FPGA-based hardware/software co-design is developed on Xilinx Virtex II Pro FPGA platform. In this study, based on the balance among the system constraints, cost, and the efficiency of estimations, the performance of different algorithm implementation schemes have been explored. The developed system successfully exhibits the robustness in the chirplet signal decomposition of experimental signals. This type of study addresses a broad range of applications including velocity measurement, target detection, deconvolution, object classification, data compression, and pattern recognition. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Design space exploration for field programmable compressor trees

Design space exploration for field programmable compressor t...

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Embedded Systems Week 2008 - 2008 international Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08

作者： Niaki, Seyed Hosein Attarzadeh Cevrero, Alessandro Brisk, Philip Nicopoulos, Chrysostomos Gurkaynak, Frank K. Leblebici, Yusuf Lenne, Paolo Royal Institute of Technology School of Information and Communication Technology Stockholm Sweden Ecole Polytechnique Federale de Lausanne School of Engineering Lausanne CH-1015 Switzerland Ecole Polytechnique Federale de Lausanne School of Computer and Communication Sciences Lausanne CH-1015 Switzerland Swiss Federal Institute of Technology Zurich Microelectronics Design Center Zurich CH-8092 Switzerland

ISBN: (纸本)9781605584690

The field programmable Compressor Tree (FPCT) is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an FPGA or other reconfigurable device. This paper presents a design space exploration (DSE) method that can be used to identify the best FPCT architecture for a given set of arithmetic benchmark circuits;in practice, an FPGA vendor can use the design space exploration to tailor the FPCT to meet the needs of the most important benchmark circuits of the vendor's largest-volume clients. One novel feature of the DSE is the introduction of a metric called I/O utilization;we found that I/O utilization has a strong correlation with both the critical path delay and area of the benchmark circuits under study. Pruning the search space using I/O utilization allowed us to reduce significantly the number of FPCTs that must be synthesized and evaluated during the DSE, while giving high confidence that the best architectures are still explored. The DSE was applied to seven small-to-medium range benchmark circuits;one FPCT architecture was found that was 30% faster than the second best in terms of critical path delay, and only 3.34% larger than the smallest. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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MOTIM: An industrial application using nocs 08

MOTIM: An industrial application using nocs

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21st symposium on Integrated Circuits and Systems Design, SBCCI 2008

作者： Moraes, Fernando G. Carara, Everton A. Pigatto, Daniel V. Calazans, Ney L. PUCRS FACIN Av. Ipiranga 6681 Porto Alegre - 90619-900 Brazil DATACOM TELEMÁTICA Av. França 735 Porto Alegre - 90230-220 Brazil

ISBN: (纸本)9781605582313

High-speed networks used to interconnect computers advance at an extraordinary pace, driven by the evolution of several contributing technologies. Due to the ever-increasing complexity of designing parts and equipments for these networks, design complexity management makes scalability and reusability more important issues than performance, in most cases. This paper describes MOTIM, a scalable and reusable architecture enabling the implementation of Ethernet switches with low latency and high throughput. The architecture is built around a network-on-chip-based switch fabric, which guarantees scalability. The architecture has been validated by functional simulation and prototyped in FPGAs. The experimental results show that even under severe traffic conditions the architecture achieves packet transmission with low latencies. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Dynamic tuning of configurable architectures: The AWW online algorithm 08

Dynamic tuning of configurable architectures: The AWW online...

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Embedded Systems Week 2008 - 6th IEEE/acm/IFIP international Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

作者： Huang, Chen Sheldon, David Vahid, Frank Department of Computer Science and Engineering University of California Riverside United States Center for Embedded Computer Systems UC Irvine United States

ISBN: (纸本)9781605584706

Architectures with software-writable parameters, or configurable architectures, enable runtime reconfiguration of computing platforms to the applications they execute. Such dynamic tuning can improve application performance, as well as energy. However, reconfiguring incurs a temporary performance cost. Thus, online algorithms are needed that decide when to reconfigure and which configuration to choose such that overall performance is optimized. We introduce the adaptive weighted window (AWW) algorithm, and compare with several other algorithms, including algorithms previously developed by the online algorithm community. We describe experiments showing that AWW results are within 4% of the offline optimal on average. AWW outperforms the other algorithms, and is robust across three datasets and across three categories of application sequences too. AWW improves a non-dynamic approach on average by 6%, and by up to 30% in low-reconfiguration-time situations. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Fault-tolerance in FPGA's through CRC voting 08

Fault-tolerance in FPGA's through CRC voting

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21st symposium on Integrated Circuits and Systems Design, SBCCI 2008

作者： Castro, Helano Coelho, Alexandre Augusto Silveira, Ricardo Jardel LESC UFC Campus Do Pici SN B 723 Fortaleza CE Brazil

ISBN: (纸本)9781605582313

The use of FPGA's for implementing fault-tolerant systems (FTS) has been widely discussed. Many FTS's have been proposed in this context and TMR is by far the most used architecture. However, those implementations have to count on the memory configuration's integrity of those FPGA's, since all the TMR's circuitry is stored into it. In fact, radiation or even electromagnetic noise can disturb the content of the configuration memory, with disastrous results for the system. In this paper we propose a way of dealing with this problem by using the FPGA's CRC as its signature. In case of an error derived from a kind of fault mentioned above, that signature will change. By voting those signatures in TRM architectures we can not only detect the faults, but we can recover from them by copying the memory configuration of a faultless FPGA into a faulty one. We discuss the difficulties of implementing this technique and the workarounds used to get over those difficulties. Finally we implement an experiment to validate the idea. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Amplifying embedded system efficiency via automatic instruction fusion on a post-manufacturing reconfigurable architecture platform

Amplifying embedded system efficiency via automatic instruct...

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9th international symposium on Quality Electronic Design

作者： Cheng, Allen C. Univ Pittsburgh Adv Comp Technol Lab Dept Elect & Comp Engn Pittsburgh PA 15260 USA

ISBN: (纸本)9780769531175

Portable embedded SoC processor architects are constantly challenged by exponentially increasing demand for newer functionality, faster real-time communication, stronger security, and higher reliability;while the constraint on energy, feature size, NRE cost, and time-to-market (TTM) grows tighter than ever. Existing approaches attempting to achieve these mutual conflicting design goals rely heavily on adopting special-purpose accelerators (SPA) to take charge of the heavy lifting in the aimed embedded SoC designs. These SPAs, synthesized from either ASIC or FPGA, are usually augmented to the base processor as co-processors to execute the performance-critical regions of applications. ASIC-based SPAs achieve performance-energy efficiency at the expense of sacrificing post-manufacturing programmability while incurring large NRE and TTM;FPGA-based SPAs retain programmability at the expense of significant energy and area increase. Furthermore, augmenting these SPAs as co-processors adds considerable communication and synchronization overhead severely compromising their initially promised benefits. This paper proposes an innovative design paradigm that moves away from the common scheme of adding co-processing ASIC/FPGA SPAs to an integrated and reconfigurable design. Specifically, we propose a new class of embedded processor by replacing the processor's conventional ALU with a more powerful and flexible Versatile Processing Unit (VPU). VPU enables multiple interdependent instructions to be fused and processed together as a single atomic VPU instruction by exploring dataflow dependencies of the application code. The instruction fusion is automatically performed by a VPU-aware compiler. The optimized VPU code reduces code size and amplifies the effective processor bandwidth and capacity by eliminating transient computation and register spill code. Experimental results show up to 400% and average 150% speedup for MediaBench with negligible area increase.

关键词： field programmable gate arrays (FPGA)

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Optimus: Efficient realization of streaming applications on FPGAs

Optimus: Efficient realization of streaming applications on ...

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Embedded Systems Week 2008 - 2008 international Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08

作者： Hormati, Amir Kudlur, Manjunath Mahlke, Scott Bacon, David Rabbah, Rodric Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States IBM T.J. Watson Research Center Hawthorne NY United States

ISBN: (纸本)9781605584690

In this paper, we introduce Optimus: an optimizing synthesis compiler for streaming applications. Optimus compiles programs written in a high level streaming language to either software or hardware implementations. The compiler uses a hierarchical compilation strategy that separates concerns between macro- and micro-functional requirements. Macro-functional concerns address how components (modules) are assembled to implement larger more complex applications. Micro-functional issues deal with synthesis issues of the module internals. Optimus thus allows software developers who lack deep hardware design expertise to transparently leverage the advantages of hardware customization without crossing the semantic gap between high level languages and hardware description languages. Optimus generates streaming hardware that achieves on average 40x speedup over our baseline embedded processor for a fraction of the energy. Additionally, our results show that streaming-specific optimizations can further improve performance by 255% and reduce the area requirements by 16% in average. These designs are competitive with Handel-C implementations for some of the same benchmarks. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA 08

Implementation of a double-precision multiplier accumulator ...

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21st symposium on Integrated Circuits and Systems Design, SBCCI 2008

作者： Barros, Abner Correa Medeiros, Victor Wanderley Costa Souza, Viviane Lucy Santos Nascimento, Paulo Sérgio Brando Mazer, Ângelo L. Barbosa, João P. F. Neves, Bruno P. Santos, Ismael De Lima, Manoel Eusebio Informatics Center Recife-PE Brazil Centro de Pesquisa da Petrobrás CENPES Petrobrás - Rio Brazil

ISBN: (纸本)9781605582313

Recently, the manufactures of supercomputers have made use of FPGAs to accelerate scientific applications [16][17]. Traditionally, the FPGAs were used only on non-scientific applications. The main reasons for this fact are: the floating-point computation complexity;the FPGA logic cells are not sufficient for the scientific cores implementation;the cores complexity prevents them to operate on high frequencies. Nowadays, the increase of specialized blocks availability in complex operations, as sum and multiplier blocks, implemented directly in FPGA and, the increase of internal RAM blocks (BRAMs) have made possible high performance systems that use FPGA as a processing element for scientific computation [2]. These devices are used as co-processors that execute intensive computation. The emphasis of these architectures is the exploration of parallelism present on scientific computation operations and data reuse. In major of these applications, the scientific computation uses, in general, operations of big floating-point dense matrices, which are normally operated by MACs. In this work, we describe the architecture of an accumulative multiplier (MAC) in double precision floating-point, according to IEEE-754 standard and we propose the architecture of a multiplier of matrices that uses developed instances of the MACs and explores the reuse of data through the use of the BRAMs (Blocks of RAM internal to the FPGAs) of a Xilinx Virtex 4 LX200 FPGA. The synthesis results showed that the implemented MAC could reach a performance of 4GFLOPs. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Fourteenth acm/sigda international symposium on field programmable gate arrays - FPGA 2006

Fourteenth ACM/SIGDA International Symposium on Field Progra...

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

ISBN: (纸本)1595932925

The proceedings contain 22 papers. The topics discussed include: embedded floating-point units in FPGAs;measuring the gap between FPGAs and ASICs;optimality study of logic synthesis for LUT-based FPGAs;improvements to technology mapping for LUT-based FPGAs;improving performance and robustness of domain-specific CPLDs;design, implementation, and verification of active cache emulator (ACE);modeling and data-dependent performance of pattern-matching architectures;yield enhancements of design-specific FPGAs;FGPA clock network architecture: flexibility vs. area and power;a reconfigurable hardware based embedded scheduler for buffered crossbar switches;and combining module selection and resource sharing for efficient FPGA pipeline synthesis.

关键词： field programmable gate arrays

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Efficient tiling patterns for reconfigurable gate arrays 08

Efficient tiling patterns for reconfigurable gate arrays

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proceedings of the 16th international acm/sigda symposium on field programmable gate arrays

作者： Sumanta Chaudhuri Jean-Luc Danger Philippe Hoogvorst Sylvain Guilley ENST Paris France

ISBN: (纸本)9781595939340

This article does a purely mathematical analysis based on generic models, and the idea is to investigate the possibility of using tiling patterns other than Manhattan grid in FPGAs. The goal of our research is to evolve FPGA architectures with advances in technology, and specifically better utilization of available interconnect layers. We propose a method to evaluate tiling patterns based on the first principles ( i.e Rent's Rule, Donath's result, equivalence of wire flux and wire length). We show that, use of tiling patterns formed with higher order polygons can improve the speed and area performances of an FPGA. This gain is highly dependent on depopulation schemes and other parameters. However for generic tiling patterns with crossbar switchboxes there is a 22% gain in area for the hexagonal tiling pattern, and a 30% gain in area for the octagonal tiling pattern. Moreover the average interconnect length is around 15% lesser for hexagonal and 31% lesser for the octagonal tiling compared to square tiling. We can expect a proportional increase in speed. We also present a comparative plot of total interconnect lengths for these tiling patterns and the hierarchical gate arraysThe physical realizability of these tiling patterns in CMOS are to be investigated. We present a layout scheme for both hexagonal and octagonal FPGAs. To our knowledge standard processes support 45° metal lines, whereas 60° lines can be etched using non-standard processes. We must keep in mind, that in practice one must use some sort of depopulation and staggering scheme, and these results provide only an idea of gains that can be achieved. The actual interconnect structure is of course dependent on several factors (i.e available interconnect layers, difficulty of fabrication, required speed/area, evolution of CMOS technology etc). Our future research direction will be to choose an efficient interconnect strategy based on this and previous researches, as well as experimental results

关键词： tiling interconnect FPGA hexagonal octagonal

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