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acm/sigda international symposium on field programmable gate arrays - FPGA 2006年 iii页

作者： Wilton, Steve DeHon, Andre University of British Columbia Canada California Institute of Technology United States

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A Synthesizable Datapath-Oriented Embedded FPGA Fabric 07

A Synthesizable Datapath-Oriented Embedded FPGA Fabric

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15th acm/sigda international symposium on field-programmable gate arrays

作者： Wilton, Steve J. E. Ho, C. H. Leong, Philip H. W. Luk, Wayne Quinton, Brad Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781595936004

We present an architecture for a synthesizable datapath-oriented field programmable gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a System-on-Chip (SoC). Our architecture is optimized for bus-based operations that are common in signal processing and computation intensive applications. It employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. We also describe a proof-of-concept layout of our core. It is shown that the proposed architecture is significantly more area efficient than the best previously reported synthesizable programmable logic core.

关键词： field programmable gate Array Datapath Synthesis Integrated Circuit System-on-Chip Embedded Block

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GlitchLess: An Active Glitch Minimization Technique for FPGAs 07

GlitchLess: An Active Glitch Minimization Technique for FPGA...

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15th acm/sigda international symposium on field-programmable gate arrays

作者： Lamoureux, Julien Lemieux, Guy G. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781595936004

This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable delay elements within the logic blocks of an FPGA to programmably align the arrival times of early-arriving signals to the inputs of the lookup tables and to filter out glitches generated by earlier circuitry. On average, the proposed technique eliminates 91% of the glitching, which reduces overall FPGA power by 18%. The added circuitry increases overall area by 5% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires no modifications to the existing FPGA routing architecture or CAD flow.

关键词： field-programmable gate arrays Power Minimization

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Design of a Logic Element for Implementing an Asynchronous FPGA 07

Design of a Logic Element for Implementing an Asynchronous F...

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15th acm/sigda international symposium on field-programmable gate arrays

作者： Smith, Scott C. Univ Missouri Dept Elect & Comp Engn Rolla MO 65462 USA

ISBN: (纸本)9781595936004

A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and can utilize embedded registration for gates with three or fewer inputs. The developed LE is compared with a previous NCL LE, showing that the one developed herein yields a more area efficient NCL circuit implementation. The NCL FPGA logic element is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process.

关键词： Asynchronous logic design delay-insensitive circuits field programmable gate Array (FPGA) NULL Convention Logic (NCL) reconfigurable logic

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Reconfigurable Finite field Instruction Set Architecture

Reconfigurable Finite Field Instruction Set Architecture

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15th acm/sigda international symposium on field-programmable gate arrays

作者： Jachimiec, Nathan Martinez-Vallina, Fernando Saniie, Jafar IIT Embedded Comp & Signal Proc Res Grp Chicago IL 60616 USA

ISBN: (纸本)9781595936004

Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite field instruction set extensions and a reconfiguration framework have been constructed to enable a finite field multiplier to be regenerated via software control. A performance evaluation has been created by generating a Finite field Extensions Unit with MicroBlaze processor in a Xilinx Virtex(2)Pro FPGA. By utilizing the in-system partial reconfiguration capability, the finite field multiplier can be customized to a particular size and definition. With a customized GF(2(163)) multiplier, a speed-up factor of 1530x has been demonstrated versus execution of the same algorithm on the MicroBlaze processor alone.

关键词： Finite field Arithmetic Galois fields Instruction Set Extensions Xilinx MicroBlaze Fast Simplex Links FSL Embedded Development Partial Reconfiguration

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FPGA 2001: Fifteenth acmIsigda international symposium on field-programmable gate arrays

FPGA 2001: Fifteenth ACMISIGDA International Symposium on Fi...

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FPGA 2007: Fifteenth acm/sigda international symposium on field-programmable gate arrays

ISBN: (纸本)1595936009

The proceedings contain 25 papers. The topics discussed include: a routing fabric for monolithically stacked 3D-FPGA;design of a logic element for implementing an asynchronous FPGA;designing efficient input interconnect blocks for LUT clusters using counting and entropy;a synthesizable datapath-oriented embedded FPGA fabric;a versatile, low latency HyperTransport core;an FPGA-based Pentium in a complete desktop system;a 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA;variation-aware routing for FPGAs;stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation;post-route LUT output polarity selection for timing optimization;synthesis of an application-specific soft multiprocessor system;FPGA-friendly code compression for horizontal microcoded custom IPs;and a practical FPGA-based framework for novel CMP research.

关键词： field programmable gate arrays (FPGA)

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Post-Placement Leakage Optimization for Partially Dynamically Reconfigurable FPGAs

Post-Placement Leakage Optimization for Partially Dynamicall...

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12th international symposium on Low Power Electronics and Design

作者： Li, Chi-Feng Yuh, Ping-Hung Yang, Chia-Lin Chang, Yao-Wen Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei 106 Taiwan

ISBN: (纸本)9781595937094

As technology continues to shrink, leakage power becomes an important issue for modern FPGAs. In this paper, we address the leakage issue of partially dynamical reconfigurable FPGAs. We focus on eliminating leakage waste due to the delay between reconfiguration and task execution. We propose a post-placement leakage-aware scheduling algorithm that refines a placement generated by a performance-driven scheduler such that leakage waste is minimized and performance is not sacrificed. Experimental results on real and synthetic designs demonstrate the effectiveness and efficiency of our algorithm on leakage optimization.

关键词： Leakage field-programmable gate Array Scheduling Post-placement Optimization

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NoC-based FPGA: Architecture and routing

NoC-based FPGA: Architecture and routing

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1st international symposium on Networks-on-Chip

作者： Gindin, Roman Cidon, Israel Keidar, Idit Technion Israel Inst Technol Dept Elect Engn IL-32000 Haifa Israel

ISBN: (纸本)9780769527734

We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instances with good performance and low cost. Our architecture minimizes the cost of supporting a wide range of design instances with given throughput requirements by balancing the amount of efficient hard-coded NoC infrastructure and the allocation of "soft" networking resources at configuration time. Although traffic patterns are design-specific, the physical link infrastructure is a performance bottleneck, and hence should be hard-coded. It is therefore important to employ routing schemes that allow for high flexibility to efficiently accommodate different traffic patterns during configuration. We examine the required capacity allocation for supporting a collection of typical traffic patterns on such chips under a number of routing schemes. We propose a new routing scheme, Weighted Ordered Toggle (WOT), and show that it allows high design flexibility with low infrastructure cost. Moreover, WOT utilizes simple, small-area, on-chip routers, and has low memory demands.

关键词： field programmable gate arrays (FPGA)

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SEU-Mitigation placement and routing algorithms and their impact in SRAM-based FPGAs

SEU-Mitigation placement and routing algorithms and their im...

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8th international symposium on Quality Electronic Design

作者： Zarandi, Hamid R. Miremadi, Seyed G. Pradhan, Dhiraj K. Mathew, Jimson Sharif Univ Technol Dept Comp Engn Tehran Iran Univ Bristol Dept Comp Sci Bristol Avon England

ISBN: (纸本)9780769527956

In this paper, we propose a new SEU-mitigative placement and routing of circuits in the FPGAs which is based on the popular VPR tool. The VPR tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation. Moreover, no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. Using the modified tool, i.e., S-VPR, the role of placement and routing algorithms on the fault-tolerance of circuits implemented on FPGAs is achieved. The secondary propose of this paper is to find which of placement or routing is more suited for decreasing SEU sensibility of circuits and to find whether these SEU sensibility reductions are cumulative or not when they applied in sequence. We have investigated the effect of S-VPR on several MCNC benchmarks and the results of the placement and routing have been compared to the traditional one. The evaluations of results show that placement and routing can decrease the SEU rate of circuits implemented on FPGAs about 18% and 12%, respectively. However, it increases critical path delay and power consumptions of the circuits up to 5% and 8%, respectively. This means that without any redundancies, just by means of fault-avoidance method, mitigation of SEU effects would decrease up to 22% significantly and this method is notable compared to previous TMR and DWC mechanisms.

关键词： field programmable gate arrays (FPGA)

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Dynamically optimizing FPGA applications by monitoring temperature and workloads

Dynamically optimizing FPGA applications by monitoring tempe...

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20th international Conference on VLSI Design held jointly with the 6th international Conference on Embedded Systems

作者： Jones, Phillip H. Cho, Young H. W. Lockwood, John Washington Univ Appl Res Lab St Louis MO 63130 USA

ISBN: (纸本)9780769527628

In the past, field programmable gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed excessive power Today, the temperature of FPGAs are a major concern due to increased logic density and speed. Large applications with highly pipelined datapaths can ultimately generate more heat than the package can dissipate. For FPGAs that operate in controlled environments, heat sinks and fans can be used to effectively dissipate heat from the device. However, FPGA devices operating under harsher thermal conditions in outdoor environments, or in systems with malfunctioning cooling systems need a thermal management control system. To address this issue, we had previously devised a reconfigurable temperature monitoring system that gives feedback to the FPGA circuit using the measured junction temperature of the device. Using this feedback, we designed a novel dual frequency switching system that allows the FPGA circuits to maintain the highest level of throughput performance for a given maximum junction temperature. This paper extends the previous work by additionally making this adaptive frequency mechanism workload aware and evaluating power and latency performance under bursty workload conditions. Our working system has been implemented on the field programmable Port Extender (FPX) platform developed at Washington University in St. Louis. Experimental results with a scalable image correlation circuit show up to a 30% saving in power for bursty workloads and up to a 2x factor improvement in latency performance as compared to a system without thermal or workload feedback. Our circuit provides power efficient high performance processing of bursty workloads, while ensuring the device always operates within a safe temperature range.

关键词： field programmable gate arrays (FPGA)

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