检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

804 篇 会议
30 篇 期刊文献

馆藏范围

834 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

671 篇 工学
- 617 篇 计算机科学与技术...
- 358 篇 软件工程
- 275 篇 电子科学与技术（可...
- 203 篇 电气工程
- 114 篇 信息与通信工程
- 45 篇 控制科学与工程
- 42 篇 动力工程及工程热...
- 34 篇 机械工程
- 23 篇 生物工程
- 14 篇 仪器科学与技术
- 13 篇 建筑学
- 12 篇 土木工程
- 11 篇 冶金工程
- 10 篇 化学工程与技术
- 10 篇 生物医学工程（可授...
- 8 篇 材料科学与工程（可...
- 6 篇 光学工程
- 4 篇 农业工程
243 篇 理学
- 195 篇 数学
- 40 篇 物理学
- 24 篇 生物学
- 23 篇 统计学（可授理学、...
- 10 篇 系统科学
- 7 篇 化学
72 篇 管理学
- 61 篇 管理科学与工程(可...
- 40 篇 工商管理
- 12 篇 图书情报与档案管...
19 篇 经济学
- 19 篇 应用经济学
16 篇 法学
- 14 篇 社会学
4 篇 教育学
- 4 篇 教育学
4 篇 农学
2 篇 医学

主题

371 篇 field programmab...
265 篇 field programmab...
48 篇 signal processin...
48 篇 clocks
45 篇 modulation
45 篇 ofdm
45 篇 estimation
44 篇 filtration
30 篇 fpga
22 篇 hardware
17 篇 routing
14 篇 computer archite...
14 篇 switches
13 篇 table lookup
11 篇 logic arrays
9 篇 prototypes
9 篇 systolic arrays
9 篇 optimization
9 篇 field-programmab...
9 篇 high-level synth...

机构

6 篇 univ of toronto ...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 imperial college...
4 篇 xilinx
4 篇 stanford univ st...
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 university of ca...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 department of co...

作者

21 篇 cong jason
20 篇 rose jonathan
11 篇 betz vaughn
10 篇 hauck scott
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 zhang zhiru
9 篇 chen deming
8 篇 wilton steven j....
8 篇 schmit herman
7 篇 constantinides g...
7 篇 chow paul
7 篇 langhammer marti...
6 篇 anderson jason h...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
5 篇 so hayden kwok-h...
5 篇 dehon andre
5 篇 cheung peter y. ...

语言

827 篇 英文
7 篇 其他

检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 834 条记录，以下是511-520 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Prototyping globally Asynchronous locally synchronous circuits on commercial synchronous FPGAs

Prototyping globally Asynchronous locally synchronous circui...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Najibi, Mehrdad Saleh, Kamran Naderi, Mohsen Pedram, Hossein Sedighi, Mehdi 424 Hafez Ave. Tehran 15785 Iran

This paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to successfully implement a GALS circuit on FPGA are discussed. The library includes clock generators and arbiters, and different port controllers. Different implementations of these circuits and their advantages and disadvantages are explored. At the end we present a GALS Reed-Solomon decoder as a practical example. The results show that the GALS approach improves the performance of the circuit by 11% and reduces the power consumption by 18.7% to 19.6% considering different error rates. On the other hand, the area of the circuit is increased by 51% which is acceptable considering that a pure synchronous circuit including a central controller is decomposed to generate GALS system and 29% of this overhead belongs to distributing controller in different modules. Deploying better decomposition methods can reduce this overhead substantially.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping

An FPGA based SDRAM controller with complex QoS scheduling a...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Heithecker, Sven Ernst, Rolf Institute for Computer and Communication Network Engineering Technical University of Braunschweig Braunschweig Germany

Today high-end video and multimedia processing applications require huge amounts of memory. For cost reasons, the usage of conventional dynamic RAM (SDRAM) is preferred. However, SDRAM access optimization is a complex task, especially if multi-stream access with different QoS (Quality of Service) requirements is involved. At SIPS 2003 conference, we presented a multi-stream DDR-SDRAM controller IP covering combinations of low latency requirements for processor cache access, hard real-time constraints for periodic video signals and hard real-time bursty accesses for video coprocessors. To handle these contradictory QoS requirements at high system performance, a combination of an 2-stage scheduling algorithm and static priorities was used. This poster describes an additional flow control which greatly enhances the overall performance and controlability. The efficient but simple controller design makes the controller well suited for FPGA based designs. Experiments with our FPGA based high-end video platform demonstrate the superiority of this architecture.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Hyper customized processors for bio-sequence database scanning on FPGAs 05

Hyper customized processors for bio-sequence database scanni...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Oliver, Tim Schmidt, Bertil Maskell, Douglas Centre for High Performance Embedded Systems Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781595930293

Protein sequences with unknown functionality are often compared to a set of known sequences to detect functional similarities. Efficient dynamic-programming algorithms exist for solving this problem, however current solutions still require significant scan times. These scan time requirements are likely to become even more severe due to exponential database growth. In this paper we present a new approach to bio-sequence database scanning using re-configurable FPGA-based hardware platforms to gain high performance at low cost. Efficient mappings of the Smith-Waterman algorithm using fine-grained parallel processing elements (PEs) that are tailored towards the parameters of a query have been designed. We use customization opportunities available at run-time to dynamically hyper customize the systolic array to make better use of available resource. Our FPGA implementation achieves a speedup of approximately 170 for linear gap penalties and 125 for affine gap penalties as compared to a standard desktop computing platform. We show how hyper-customization at run-time can be used to further improve the performance. Copyright 2005 acm.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

CUSP: A modular framework for high speed network applications on FPGAs

CUSP: A modular framework for high speed network application...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Schelle, Graham Grunwald, Dirk Computer Science University of Colorado at Boulder Boulder CO

For several years now, modern FPGAs have included onchip network related hard cores. These cores include Xilinx's RocketIO and Altera's RapidIO serial transceivers. However, to use these cores in a complete networking application may be a daunting task to a non-networking expert. In addition to the complicated use of these components, the high performance needs of modern networking applications require designs that are optimized for low latency and a moderately high clock rate. Therefore to meet these challenges, we present CUSP (Click Utilizing Speculation and Parallelism) for reconfigurable hardware platforms. Click is an accepted software network router framework that is similar to CUSP, but specifically built for a Linux platform and software network routers. CUSP, while also having a modular design of reusable components, additionally provides automated speculation and parallelism to gain better performance on FPGAs. An accompanying scripting language allows quick creation of these routers from a body of existing components. We have implemented an example network application through the CUSP design flow and its performance will be compared against alternative network design methods. Copyright 2005 acm.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration

Efficient methodology for detection and correction of SEU-ba...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Reddy, E. Syam Sundar Chandrasekhar, Vikram Sashikanth, M. Kamakoti, V. Narayanan, Vijaykrishnan Dept. of Computer Science and Engineering Indian Institute of Technology Madras Chennai - 600036 India Department of Computer Science and Engineering Pennsylvania State University University Park PA 16802 United States

This paper proposes a new CLB architecture for FPGAs and associated testing and reconfiguration techniques that detect single routing/interconnect errors and correct them using partial reconfiguration. The results of error detection are propagated to a single output port by a chain-like shift register, which are used to reduce the segment of the routing architecture that has to be reconfigured. The error is corrected by partially reconfiguring the above minimal segment alone, thereby reducing the time for reconfiguration. The proposed testing technique detects all possible routing errors that affects the logic of the circuit, including bridging faults. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA. Empirically, our technique detected all single interconnect errors in benchmark circuits. In addition, for the majority of errors, our correction technique required less than 10% of the switch matrices to be reconfigured to correct the errors.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

3D FPGAs: Placement, routing, and architecture evaluation

3D FPGAs: Placement, routing, and architecture evaluation

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Ababei, Cristinel Mogal, Hushrav Bazargan, Kia Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN 55455

This paper introduces a novel 3-Dimensional (3D) vertically integrated adaptive computing system. This 3D-SoftChip is a combination of state-of-the-art processing and interconnection technology. It comprises the vertical integration of two chips (a Configurable Array Processor and an Intelligent Configurable Switch) through indium bump 3D interconnections. The Configurable Array Processor (CAP) is an array of heterogeneous processing elements (PEs) while the Intelligent Configurable Switch (ICS) comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer along with a Direct Memory Access (DMA) controller. This paper introduces the 3D-Softchip architecture for real-time communication and multimedia signal processing as a next gene! ration computing system. The paper further describes the up-to-date HW/SW co-design and verification methodology including high level system modeling and architecture exploration of 3D-SoftChip using SystemC in order to determine the optimum hardware specification in the early design stage.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Efficient packet classification for network intrusion detection using FPGA 05

Efficient packet classification for network intrusion detect...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Song, Haoyu Lockwood, John W. Department of CSE Washington University St. Louis United States

ISBN: (纸本)9781595930293

FPGA technology has become widely used for real-time network intrusion detection. In this paper, a novel packet classification architecture called BV-TCAM is presented, which is implemented for an FPGA-based Network Intrusion Detection System (NIDS). The classifier can report multiple matches at gigabit per second network link rates. The BV-TCAM architecture combines the Ternary Content Addressable Memory (TCAM) and the Bit Vector (BV) algorithm to effectively compress the data representations and boost throughput. A tree-bitmap implementation of the BV algorithm is used for source and destination port lookup while a TCAM performs the lookup of the other header fields, which can be represented as a prefix or exact value. The architecture eliminates the requirement for prefix expansion of port ranges. With the aid of a small embedded TCAM, packet classification can be implemented in a relatively small part of the available logic of an FPGA. The design is prototyped and evaluated in a Xilinx FPGA XCV2000E on the FPX platform. Even with the most difficult set of rules and packet inputs, the circuit is fast enough to sustain OC48 traffic throughput. Using larger and faster FPGAs, the system can work at speeds greater than OC192. Copyright 2005 acm.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Dual-Vt FPGA design for leakage power reduction

Dual-Vt FPGA design for leakage power reduction

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Kumar, Akhilesh Anis, Mohab Electrical and Computer Engineering University of Waterloo Waterloo Ont. N2L 3G1

Leakage power has been overshadowed by dynamic power minimization techniques in FPGAs, and is a growing concern in programmable logic. This paper proposes a dual threshold voltage implementation of the FPGA architecture for leakage power reduction. A CAD flow is developed for assigning high threshold voltage to the logic elements within the logic blocks of the FPGA for leakage power reduction. The CAD flow ensures that all the logic blocks remain identical with respect to the number of high and low threshold voltage logic elements that each logic block contains. This CAD flow leads to a dual threshold voltage implementation for the FPGA architecture. Results indicate that over 95% of the logic elements in the FPGA can be assigned high threshold voltage. On an average leakage savings of 60% and up to 70% for some benchmarks can be achieved. The proposed CAD flow forms a basis on which other dual threshold voltage implementations of FPGA can be evaluated. We investigate the design trade-offs between the ratio of the number of high and number of low-Vt logic elements in a cluster and the leakage savings. We also investigate the impact of cluster size on leakage savings for the dual threshold voltage implementation.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Skew-programmable clock design for FPGA and skew-aware placement 05

Skew-programmable clock design for FPGA and skew-aware place...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Yeh, Chao-Yang Marek-Sadowska, Malgorzata ECE Department University of California Santa Barbara CA 93106 United States

ISBN: (纸本)9781595930293

In this paper, we propose a skew-programmable clock-routing architecture. The skews can be adjusted using programmable delay elements (PDEs) which we insert into the clock trees. We develop efficient, shortest-path-based algorithms for programming PDEs to optimize timing. Unlike previous methods for FPGA skew optimization which require large power and routing penalty, our method can achieve large timing improvement with small overhead. Typically, if timing requirements are tight, placers make efforts to satisfy them, often at a cost of compromising routability, total wire length, and power. In this work, we propose novel clock-skew-aware placement algorithms which allow us to relax the timing constraints during placement. Timing can be later optimized as a post process. Even though we demonstrate the efficiency of our approach using FPGAs, the new skew optimization method and the new placement algorithm are quite general and can be applied to any general, topology-constrained skew optimization problem. Experimental results indicate that using the new clock-architecture we can obtain a 22% timing improvement for post-layout skew optimization and an additional 21% improvement from our skew-aware placement algorithm. In one fabric, the cost of added logic is 2.19% as measured by dynamic power dissipation, and 0.85% in terms of area overhead. Copyright 2005 acm.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Domain specific non-uniform routing architecture for embedded programmable IP core 05

Domain specific non-uniform routing architecture for embedde...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Wen, Yujie Tong, Jiarong Chiang, Charles State Key Lab of ASIC and System Fudan University Shanghai China Synopsys Inc. Mountain View CA 94043

ISBN: (纸本)9781595930293

Non-uniform routing architecture contains routing channels of different widths. In this paper we propose a design methodology of domain specific non-uniform programmable routing architecture for embedded programmable IP cores. This non-uniform architecture is based on symmetrical FPGA model and consists of connection boxes of full connectivity and rectangular switch boxes. The rectangular switch box is derived from universal switch box module. Area and timing efficiency of the proposed architecture is compared with those of uniform architecture based on placement and routing result over a set of MCNC benchmark circuits. The comparison results show that non-uniform routing architecture gains up to 8% layout area reduction from uniform ones. Besides, by widening some of the routing channels where routing congestions accumulate, the average critical path delay of non-uniform architecture is 8% less than that of uniform one while maintain the same area.

关键词： Embedded systems

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共84页 << < 48 49 50 51 52 53 54 55 56 57 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：