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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Energy-efficient FPGA interconnect architecture design

Energy-efficient FPGA interconnect architecture design

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Krishnan, Rohini Meijer, R.I.M.P. Guillaume, Durand Philips Research Laboratories Eindhoven Netherlands Intel Corporation United States

In this work, the design of an energy-efficient FPGA interconnect architecture has been investigated. It concerns a dual-supply solution, where the logic blocks are powered by a nominal voltage supply and the interconnect part is powered by a reduced voltage supply. The behaviour of a fully-buffered, a fully pass-transistor based and a hybrid buffer and pass-transistor architecture has been investigated over a range of power supply voltages. It is found that there exists an optimal ratio between the number of pass-transistor and tri-state buffer switches depending on the load and power supply involved. By reducing the signal voltage swing on the interconnect, the need for a fully tri-state buffer-based interconnect is eliminated, thus saving valuable area and power. Through benchmark studies, it is confirmed that using an optimal composite of pass-transistor and tri-state buffer switches operating at a reduced power supply can meet the same speed as compared to the full-swing scenario at a much lower power consumption. An average reduction in power-delay of 4.4x for low-load critical paths and 2.7x for high-load critical paths is achieved using buffer receivers. Using levelshifter receivers, an average reduction in power-delay of 4.7x for low-load critical paths and 2.8x for high-load critical paths is obtained. It is also found that due to partially replacing tri-state buffers by pass-transistor switches and inspite of using levelshifters, we can save up to a factor of 4x in interconnect area as compared to fully-buffered architectures. The results have been validated over various benchmarks in a 0.1 μm CMOS technology.

关键词： field programmable gate arrays

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Multi-GHz SiGe design methodologies for reconfigurable computing

Multi-GHz SiGe design methodologies for reconfigurable compu...

引用

2005 acm Great Lakessymposium on VLSI, GLSVLSI'05

作者： Zhou, Kuan McDonald, John F. Department of Electrical and Computer Engineering University of New Hampshire Durham NH 03824 United States Department of Electrical Computer and Systems Engineering Rensselaer Polytechnic Institute Troy NY 12180 United States

A high-speed and low-power field programmable gate Array (FPGA) is the dream of digital designers. The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz FPGAs [3, 4], In the past, high static power consumption discouraged the significant scale-up of bipolar FPGAs. This paper details new ideas to reduce power and layout area in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize novel serial dual configuration planes to achieve an efficient programmability. In addition, new layout techniques are developed to reduce the bipolar areas. Several SiGe FPGA test chips based on Xilinx 6200 and Virtex Configurable Logic Blocks (CLBs) have been fabricated for demonstration. Copyright 2005 acm.

关键词： field programmable gate arrays

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Multiple fault testing of logic resources of SRAM-based FPGAs

Multiple fault testing of logic resources of SRAM-based FPGA...

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18th international Conference on VLSI Design/4th international Conference on Embedded Systems Design

作者： Goyal, S Choudhury, M Rao, SSSP Kumar, K Indian Inst Technol Bombay 400076 Maharashtra India

ISBN: (纸本)0769522645

We shall present a simple but useful method which detects all multiple stuck-at faults in the application and configuration inputs of LUTs. A novel method for testing of stuck-at faults at control bits of flip flops has also been proposed. The aim is to integrate testing of LUTs, flip flops and multiplexers which will reduce the number of configurations and hence minimize the testing time.

关键词： field programmable gate arrays

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High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping

High-diagnosability online built-in self-test of FPGAs via i...

引用

2005 acm Great Lakessymposium on VLSI, GLSVLSI'05

作者： Suthar, Vishal Dutt, Shantanu University of Illinois at Chicago Chicago IL 60607 United States

We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for which previous BIST methods proved ineffective. Using an iterative bootstrapping process, our method first finds a fault-free test circuit in each BISTer tile and then tests the PLBs functionally using a fault-detection-and-gross-diagnosis phase followed by a time-efficient adaptive diagnosis phase. We establish the correctness of the deterministic phases of our BIST technique. We also analyze the probability of correct diagnosis by our BISTer in the presence of multiple random faults. Simulation results show that our BIST technique has very high fault coverage (98.7% for 25% fault density for random faults and 98.9% for 8.8% fault density for clustered faults) and low fault latency, and supports the theoretical analysis. Copyright 2005 acm.

关键词： field programmable gate arrays

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proceedings of ISPD'05 -2005 international symposium on Physical Design

Proceedings of ISPD'05 -2005 International Symposium on Phys...

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2005 international symposium on Physical Design, ISPD'05

The proceedings contain 41 papers. The topics discussed include: the diagnostic method of detecting and assessing the impact of physical design optimizations on routing;routing of analog busses with parasitic symmetry;coupling aware timing optimization and antenna avoidance in layer assignment;a fast algorithm for power grid design;an efficient surface-based low-power buffer insertion algorithm;multi-bend bus driven floorplanning;mapping algorithm for large-scale field programmable analog array;thermal via placement in 3D ICs;unified quadratic programming approach for mixed mode placement;a semi-persistent clustering technique for VLSI circuit placement;and evaluation of placer soboptimality via zero-change netlist transformers.

关键词： VLSI circuits

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FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks

FPGA implementation of a modular and pipelined WF scheduler ...

引用

2005 acm Great Lakessymposium on VLSI, GLSVLSI'05

作者： Merhebi, Abdallah Mohamed, Otmane Ait Department of Electrical Engineering and Computer Science University of Concordia Montréal Que. H3G 1M8 Canada

In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS) interfaces and ideal for the design of hybrid IP/ATM switches. Our contributions is an extension to an existing 4 channel scheduler architecture that combines the Highest Value First scheme and Round Robin scheme, to a modular multi channel scheduler design. The improvement we offer here compared to the previuous implementation is that we have used the existing 4 channel core module to build a higher order WF queuing system without decreasing its overall performance. As a result, our scheduler is general enough to accommodate ATM (UTOPIA Level3/4), POS Phy Level3 (or PL3 for OC48) as well as POS Phy Level4 (or PL4 for OC192) interfaces. Copyright 2005 acm.

关键词： field programmable gate arrays

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Session details: New directions for programmable devices 05

Session details: New directions for programmable devices

引用

proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： Steve Trimberger Xilinx

No abstract available.

ISBN: (纸本)9781595930293

No abstract available.

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Detecting SEU-caused routing errors in SRAM-based FPGAs

Detecting SEU-caused routing errors in SRAM-based FPGAs

引用

18th international Conference on VLSI Design/4th international Conference on Embedded Systems Design

作者： Reddy, ESS Chandrasekhar, V Sashikanth, M Kamakoti, V Vijaykrishnan, N Indian Inst Technol Dept Comp Sci & Engn Madras 600036 Tamil Nadu India

ISBN: (纸本)0769522645

This paper proposes a new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA. The proposed testing technique detects all possible routing errors including bridging faults, and requires a single configuration of only the LUTs of the FPGA. Any routing error that affects the logic of the circuit is detected by the proposed technique in a maximum of 8 clock cycles. It Is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA.

关键词： field programmable gate arrays complex logic blocks single event upset routing errors fault tolerance graph theory vertex Coloring problem

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On-line synthesis for partially reconfigurable FPGAs

On-line synthesis for partially reconfigurable FPGAs

引用

18th international Conference on VLSI Design/4th international Conference on Embedded Systems Design

作者： Huang, RQ Vermuri, R Univ Cincinnati Cincinnati OH 45220 USA

ISBN: (纸本)0769522645

An important application of dynamically and partially reconfigurable computing platforms is in dynamic task allocation and execution. On-line synthesis, on-line placement and on-line routing are the three essential steps in implementing an incoming task on the FPGA during run-time. Whereas there has been some research in on-line placement, on-line synthesis received relatively little attention. In this paper we present what is believed to be the first on-line synthesis methodology for partially reconfigurable FPGAs. In on-line synthesis time for synthesise should be kept low while ensuring the placeability of the synthesized design on the FPGA in the available empty area and meeting the performance requirements. We ensure placeability by considering and maintaining the available area on the FPGA surface as a collection of maximal empty rectangles. The proposed synthesizer allocates the FPGA resources adaptively and is incremental in nature. The algorithm is designed to be linear in terms of the number of operations to ensure its on-line usage. Our experimental results demonstrate the advantages of the proposed approach.

关键词： field programmable gate arrays

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Pinot:: Speculative multi-threading processor architecture exploiting parallelism over a wide range of granularities 38

<i>Pinot</i>:: Speculative multi-threading processor archite...

引用

38th Annual IEEE/acm international symposium on Microarchitecture

作者： Ohsawa, T Takagi, M Kawahara, S Matsushita, S NEC Corporation

ISBN: (纸本)0769524400

We propose a speculative multi-threading processor architecture called Pinot. Pinot exploits parallelism over a wide range of granularities without modifying program sources. Since exploitation of fine-grain parallelism suffers from limits of parallelism and overhead incurred by parallelization, it is better to extract coarse-grain parallelism. Coarse-grain parallelism is biased in some programs (mainly, numerical ones) and some program portions. Therefore, exploiting both coarsen and fine-grain parallelism is a key to the performance of speculative multithreading. The features of Pinot are as follows: (1) A parallelizing tool extracts parallelism at any level of granularity (e.g. even ten thousand instructions) from any program sub-structures (e.g. loops, calls, or basic blocks). The tool utilizes formulation in which the parallelization process is reduced to a combinatorial optimization problem. (2) A parallel execution model with extension of thread control instructions is designed in order to minimize the increase of the dynamic instruction count. The model employs implicit thread termination and cancellation, as well as register value transfer without synchronization. (3) A versioning cache called Version Resolution Cache (VRC) accomplishes both coarse- and fine-grained speculative multithreading. VRC operates as a large buffer for coarse-grained multi-threading. In addition, it provides low latency inter-thread communication with an update-based protocol for fine-grained multi-threading. We performed cycle-accurate simulations with 38 programs from the SPEC and MiBench benchmarks. The speedup with 4-processor-element-Pinot is up to 3.7 times, and 2.2 times on geometric mean against a conventional processor The speedup in a program (susan) drops from 3.7 to 1.6 when the speculative buffer size is limited to 256 bytes. It confirms that exploiting coarse-grain parallelism is essential to the improved performance. FPGA implementation shows 32% overhead of area and

关键词： Yarn Delay Multithreading National electric code Design optimization Termination of employment Frequency synchronization Protocols field programmable gate arrays Throughput

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