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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Post-placement C-slow retiming for the xilinx virtex FPGA

Post-placement C-slow retiming for the xilinx virtex FPGA

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Weaver, Nicholas Markovskiy, Yury Patel, Yatish Wawrzynek, John UC Berkeley Berkeley CA United States

C-slow retiming is a process of automatically increasing the throughput of a design by enabling fine grained pipelining of problems with feedback loops. This transformation is especially appropriate when applied to FPGA designs because of the large number of available registers. To demonstrate and evaluate the benefits of C-slow retiming, we constructed an automatic tool which modifies designs targeting the Xilinx Virtex family of FPGAs. Applying our tool to three benchmarks: AES encryption. Smith/Waterman sequence matching, and the LEON 1 synthesized microprocessor core, we were able to substantially increase the total throughput. For some parameters, throughput is effectively doubled.

关键词： field programmable gate arrays

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I/O placement for FPGAs with multiple I/O standards

I/O placement for FPGAs with multiple I/O standards

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Mak, Wai-Kei Dept. of Comp. Sci. and Eng. University of South Florida Tampa FL 33620 United States

In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for FPGAs that support multiple I/O standards. We derive a compact integer linear programming formulation for the constrained I/O placement problem. The size of the integer linear program derived is independent of the number of I/O objects to be placed and hence is scalable to very large design instances. For example, for a Xilinx Virtex-E FPGA, the number of integer variables required is never more than 32 and is much smaller for practical design instances. Extensive experimental results using a non-commercial integer linear program solver shows that it only takes seconds to solve the resultant integer linear program in practice.

关键词： field programmable gate arrays

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Verifying the correctness of FPGA logic synthesis algorithms

Verifying the correctness of FPGA logic synthesis algorithms

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Ratchev, Boris Hutton, Mike Baeckler, Gregg Van Antwerpen, Babette Altera Corporation 101 Innovation Drive San Jose CA 95134 United States

Though verification is significantly easier for FPGA-based digital systems than for ASIC or full-custom hardware, there are nonetheless many places for errors to occur. In this paper we discuss the verification problem for FPGAs and describe several methods for verifying end-to-end correctness of synthesis algorithms, a particularly complex portion of the CAD flow. Though the primary contribution of this paper is the analysis of the overall problem, we also give an algorithm for the automatic generation of test-vectors for simulation using information from the synthesis tool, and describe a second testing method that generates purposefully difficult designs in combination with input vectors to test them. We will show the validity of these methods by standard metrics such as simulation node-coverage and through the ability for the method to locate forced errors introduced by the synthesis tool.

关键词： field programmable gate arrays

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Using logic duplication to improve performance in FPGAs

Using logic duplication to improve performance in FPGAs

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Schabas, Karl Brown, Stephen D. Dept. of Elec. and Comp. Eng. University of Toronto Toronto Ont. Canada

The purpose of this paper is to introduce a modified packing and placement algorithm for FPGAs that utilizes logic duplication to improve performance. The modified packing algorithm was designed to leave unused basic logic elements (BLEs) in timing critical clusters, to allow potential targets for logic duplication. The modified placement algorithm consists of a new stage after placement in which logic duplication is performed to shorten the length of the critical path. In this paper, we show that in a representative FPGA architecture using .18 μm technology, the length of the final critical path can be reduced by an average of 14.1%. Approximately half of this gain comes directly from the changes to the packing algorithm while the other half comes from the logic duplication performed during placement.

关键词： field programmable gate arrays

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Reducing pin and area overhead in fault-tolerant FPGA-based designs

Reducing pin and area overhead in fault-tolerant FPGA-based ...

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Lima, Fernanda Carro, Luigi Reis, Ricardo Univ. Federal do Rio Grande do Sul PPGC - Inst. de Informatica - DELET Caixa Postal: 15064 CEP 91501-970 - Porto Alegre - RS Brazil

This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However. TMR comes with high area and power dissipation penalties. The proposed technique was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. We present some fault coverage results and a comparison with the TMR approach.

关键词： field programmable gate arrays

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Implementation of BEE: A real-time large-scale hardware emulation engine

Implementation of BEE: A real-time large-scale hardware emul...

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Chang, Chen Kuusilinna, Kimmo Richards, Brian Brodersen, Robert W. Univ. of California Berkeley Berkeley Wireless Research Center 2108 Allston Way Berkeley CA 94704 United States Tampere University of Technology Inst. of Digital and Comp. Systems P.O. Box 553 FIN-33101 Tampere Finland

This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (field programmable gate Array) based emulation engine with a capacity of 10 million ASIC (Application Specific Integrated Circuits) equivalent gates. Attainable system operation frequency can exceed 60 MHz, and the system throughput has been empirically verified to achieve 600 billion 16-bit additions per second. The emulator is custom designed to maximize the performance and resource utilization for a range of telecommunication and digital signal processing applications. With its high-speed interconnect architecture and large external I/O bandwidth, the emulator excels in prototyping real-time systems that have strict timing, logic capacity, and data rate requirements. Our development efforts are guided by such ongoing projects as ultra-wide band (UWB) and multi-channel-multi-antenna (MCMA) radio systems research.

关键词： field programmable gate arrays

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The Stratix™ routing and logic architecture

The Stratix™ routing and logic architecture

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Lewis, David Betz, Vaughn Jefferson, David Lee, Andy Lane, Chris Leventis, Paul Marquardt, Sandy McClintock, Cameron Pedersen, Bruce Powell, Giles Reddy, Srinivas Wysocki, Chris Cliff, Richard Rose, Jonathan Altera Corporation 101 Innovation Drive San Jose CA 95134 United States Altera Toronto Technology Centre 151 Bloor St W. Toronto Ont. M5S 1S4 Canada

This paper describes the Altera Stratix logic and routing architecture. The primary goals of the architecture were to achieve high performance and logic density. We give an overview of the entire device, and then focus on the logic and routing architecture. The Stratix logic architecture is based on a cluster of ten 4-input LUTs and its routing consists of staggered routing lines. We describe the development of the routing architecture, including its directional bias, its direct-drive routing which reduces both area and delay. The logic array block and logic cell design is also described, and new routing structures with in the logic array block, and logic element features are described.

关键词： field programmable gate arrays

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Architectures and algorithms for synthesizable embedded programmable logic cores

Architectures and algorithms for synthesizable embedded prog...

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Kafafi, Noha Bozman, Kimberly Wilton, Steven J.E. Dept. of Elec. and Comp. Eng. University of British Columbia Vancouver BC Canada

As integrated circuits become more and more complex, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of a "hard" layout. In this paper, we focus on an alternative approach: vendors supply a synthesizable version of their programmable logic core (a "soft" core) and the integrated circuit designer synthesizes the programmable logic fabric using standard cells. Although this technique suffers increased speed, density, and power overhead, the task of integrating such cores is far easier than the task of integrating "hard" cores into an ASIC. For very small amounts of logic, this ease of use may be more important than the increased overhead. This paper presents two synthesizable programmable logic core architectures, describes the associated place and route CAD tools, and compares the two architectures to each other, and to a "hard" programmable logic core. It also shows how these cores can be made more efficient by creating a non-rectangular architecture, an option not available to "hard" core vendors.

关键词： field programmable gate arrays

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Design of FPGA interconnect for multilevel metalization

Design of FPGA interconnect for multilevel metalization

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Rubin, Raphael DeHon, Andreá Dept. of CS 256-80 California Institute of Technology Pasadena CA 91125 United States

How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third-dimension to reduce switch requirements. Unfortunately, traditional FPGA wiring schemes are not designed to exploit these additional metal layers. We introduce an alternate topology, based on Leighton's Mesh-of-Trees, which carefully exploits hierarchy to allow additional metal layers to support arbitrary device scaling. When wiring layers grow sufficiently fast with aggregate network size (N), our network requires only O(N) area: this is in stark contrast to traditional. Manhattan FPGA routing schemes where switching requirements alone grow superlinearly in N. In practice, we show that, even for the admittedly small designs in the Toronto "FPGA Place and Route Challenge," the Mesh-of-Trees networks require 10% less switches than the standard, Manhattan FPGA routing scheme.

关键词： field programmable gate arrays

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Hardware-assisted simulated annealing with application for fast FPGA placement

Hardware-assisted simulated annealing with application for f...

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Wrighton, Michael G. DeHon, André M. California Institute of Technology Computer Science 256-80 Pasadena CA 91125 United States

To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds;late-bound, reconfigurable computing applications may demand placement times as short as microseconds. In this paper, we show how a systolic structure can accelerate placement by assigning one processing element to each possible location for an FPGA LUT from a design netlist. We demonstrate that our technique approaches the same quality point as traditional simulated annealing as measured by a simple linear wirelength metric. Experimental results look ahead to compare quality against VPR's fast placer when considering the minimum channel width required to route as the primary optimization criteria. Preliminary results from an FPGA implementation show the feasibility of accelerating simulated annealing by three orders of magnitude using this approach. This means we can place the largest design in the University of Toronto's "FPGA Placement and Routing Challenge" in around 4ms.

关键词： field programmable gate arrays

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