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Architecture evaluation for power-efficient FPGAs

Architecture evaluation for power-efficient FPGAs

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Li, Fei Chen, Deming He, Lei Cong, Jason Electrical Engineering Department University of California Los Angeles CA 90095 United States Computer Science Department University of California Los Angeles CA 90095 United States

This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contributions: (i) We develop a mixed-level FPGA power model that combines switch-level models for interconnects and macromodels for LUTs;(ii) We develop a tool that automatically generates a back-annotated gate-level netlist with post-layout extracted capacitances and delays;(iii) We develop a cycle-accurate power simulator based on our power model. It carries out gate-level simulation under real delay model and is able to capture glitch power;(iv) Using the frame work fpgaEVA-LP, we study the power efficiency of FPGAs, in 0.10um technology, under various settings of architecture parameters such as LUT sizes, cluster sizes and wire segmentation schemes and reach several important conclusions. We also present the detailed power consumption distribution among different FPGA components and shed light on the potential opportunities of power optimization for future FPGA designs (e.g., ≤ 0.10um technology).

关键词： field programmable gate arrays

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A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology

A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Guo, J.R. You, C. Zhou, K. Goda, B.S. Kraft, R.P. McDonald, J.F. Rensselaer Polytechnic Institute 110 8th St. Troy NY 12180 United States United State Military Academy West Point NY 10096 United States

This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but minimizing power consumption. The new SiGe process has traded off the circuit's performance for reduced power consumption. The power supply voltage has been reduced from 3.4 V to 2.0 V. The structure of the Basic Cell, including the Configurable Logic Block (CLB) and routing multiplexers (MUXs), has been modified so that the supply voltage reduction can be attained. Simulations have shown that the gate delay of the new Basic Cell is reduced from 130 ps in the prior design to 51 ps. The total power consumption for each Basic Cell has been reduced 94% from 71 mW to 4.2 mW. making a large scale FPGA feasible. This design is currently under fabrication for testing.

关键词： field programmable gate arrays

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Stochastic, spatial routing for hypergraphs, trees, and meshes

Stochastic, spatial routing for hypergraphs, trees, and mesh...

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Huang, Randy Wawrzynek, John DeHon, André UC Berkeley Soda Hall 1776 Berkeley CA 94720 United States Dept. of CS 256-80 California Institute Technology Pasadena CA 91125 United States

FPGA place and route is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle preventing late-bound hardware and design mapping for reconfigurable systems. Previous work showed that hardware-assisted routing can accelerate fanout-free routing on Fat-Trees by three orders of magnitude with modest modifications to the network itself. In this paper, we show how these techniques can be applied to any FPGA and how they can be implemented on top of LUT networks in cases where modification of the FPGA itself is not justified. We further show how to accommodate fanout and how to achieve comparable route quality to software-based methods. For a tree network, we estimate an FPGA implementation of our routing logic could route the Toronto Place and Route Benchmarks at least two orders of magnitude faster than a software Pathfinder while achieving within 3% of the aggregate quality. Preliminary results on small mesh benchmarks achieve within one track of vpr -fast.

关键词： field programmable gate arrays

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Placement-driven technology mapping for LUT-based FPGAs

Placement-driven technology mapping for LUT-based FPGAs

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Lin, Joey Y. Jagannathan, Ashok Cong, Jason

In this paper, we study the problem of placement-driven technology mapping for table-lookup based FPGA architectures to optimize circuit performance. Early work on technology mapping for FPGAs such as Chortle-d[14] and Flowmap[3] aim to optimize the depth of the mapped solution without consideration of interconnect delay. Later works such as Flowmap-d[7], Bias-Clus[4] and EdgeMap consider interconnect delays during mapping, but do not take into consideration the effects of their mapping solution on the final placement. Our work focuses on the interaction between the mapping and placement stages. First, the interconnect delay information is estimated from the placement, and used during the labeling process. A placement-based mapping solution which considers both global cell congestion and local cell congestion is then developed. Finally, a legalization step and detailed placement is performed to realize the design. We have implemented our algorithm in a LUT based FPGA technology mapping package named PDM (Placement-Driven Mapping) and tested the implementation on a set of MCNC benchmarks. We use the tool VPR[1][2] for placement and routing of the mapped netlist. Experimental results show the longest path delay on a set of large MCNC benchmarks decreased by 12.3% on the average.

关键词： field programmable gate arrays

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Wire type assignment for FPGA routing

Wire type assignment for FPGA routing

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Lee, Seokjin Xiang, Hua Wong, D.F. Sun, Richard Y. Dept. of Elec. and Comp. Eng. The Univ. of Texas at Austin Austin TX 78712 United States Department of Elec. and Comp. Eng. Univ. Illinois at Urbana-Champaign Urbana IL 61801 United States Xilinx Inc. 2100 Logic Drive San Jose CA 95124 United States

The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently developed FPGAs (e.g., Virtex-II), there are more versatile wire types and richer connections between them than those of the older generations of FPGAs (e.g. XC4000). To fully exploit the potential of the new routing architectures, it is beneficial to perform wire type assignment for all channels as an intermediate stage between global routing and detailed routing. In this paper, we present a wire-type assignment algorithm that is based on iteratively applying min-cost maxflow technique to simultaneously route many nets. At each stage of the network flow computation, we have guaranteed optimal result in terms of routability and delay cost. We use the routing architecture of the Virtex-II FPGAs from Xilinx as a target architecture in our experiments. Experimental results show that our algorithm outperforms the traditional sequential net-by-net approach.

关键词： field programmable gate arrays

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PipeRoute: A pipelining-aware router for FPGAs

PipeRoute: A pipelining-aware router for FPGAs

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Sharma, Akshay Ebeling, Carl Hauck, Scott Electrical Engineering University of Washington Seattle WA United States Comp. Sci. and Eng. University of Washington Seattle WA United States

We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-Delay pipelined routing problem is to find the lowest cost route between a source and sink that goes through at least N (N > 1) distinct pipelining resources. In the case of a multi-terminal pipelined signal, the problem is to find a Minimum Spanning Tree that contains sufficient pipelining resources such that the delay constraint at each sink is satisfied. We begin this work by proving that the two terminal N-Delay problem is NP-Complete. We then propose an optimal algorithm for finding a lowest cost 1-Delay route. Next, the optimal 1-Delay router is used as the building block for a greedy two terminal N-Delay router. Finally, a multi-terminal routing algorithm (PipeRoute) that effectively leverages the 1-Delay and N-Delay routers is proposed. PipeRoute's performance is evaluated by routing a set of retimed benchmarks on the RaPiD [2] architecture. Our results show that the architecture overhead incurred in routing retimed netlists on RaPiD is less than a factor of two. Further, the results indicate a possible trend between the architecture overhead and the percentage of pipelined signals in a netlist.

关键词： field programmable gate arrays

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Energy-efficient signal processing using FPGAs

Energy-efficient signal processing using FPGAs

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Choi, Seonil Scrofano, Ronald Prasanna, Viktor K. Jang, Ju-Wook Dept. of Elec. Engineering Systems University of Southern California Los Angeles CA United States Department of Electronic Engineering Sogang University Seoul Korea Republic of

In this paper, we present techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform (FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in performing these tasks. Using a Xilinx Virtex-II as the target FPGA. we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II Pro and the Texas Instruments TMS320C6415. Our evaluations are done both through estimation based on energy and latency equations and through low-level simulation. For FFT, our designs dissipated an average of 60% less energy than the design from the Xilinx library and 56% less than the DSP. Our designs showed a factor of 10 improvement over the embedded processor. These results provide concrete evidence to substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing. Further, they show that FPGAs can achieve this performance while still dissipating less energy than the other two types of devices.

关键词： field programmable gate arrays

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An FPGA architecture with enhanced datapath functionality

An FPGA architecture with enhanced datapath functionality

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Leijten-Nowak, Katarzyna Van Meerbergen, Jef L. Eindhoven University of Technology Design Automation Section Den Dolech 2 Eindhoven Netherlands Philips Research Labs Embedded Syst. Arch. on Silicon Prof Holstlaan 4 WDC3 Eindhoven Netherlands

Although FPGAs are a cost-efficient alternative for both ASICs and general purpose processors, they still result in designs which are more than an order of magnitude more costly and slower than their equivalents implemented in dedicated logic. This efficiency gap makes FPGAs less suitable for high-volume cost-sensitive applications (e.g. embedded systems). We show that the intrinsic cost of traditional general-purpose FPGAs can be reduced if they are designed to target an application domain or a class of applications only. We propose a method of the application-domain characterization and apply it to characterize DSP. A novel FPGA logic block architecture derived based on such an analysis, and which exploits properties of target applications, is presented. Its key feature is the 'mixed-level granularity' being a trade-off between fine and coarse granularity required for the implementation of datapath and random logic functions, respectively. This leads to a factor of four improvement in the LUT memory size compared to commercial FPGAs. and, assuming a standard-cell implementation, a 1.6-2.8 lower datapath mapping cost. A modified mixed-grain architecture with the ALU-like functionality reduces the LUT memory size by a factor of 16 compared to commercial FPGAs, and mapped onto standard cells has a 1.9-3.3 times higher datapath mapping efficiency. For these reasons, the proposed FPGA architectures may be an interesting alternative to the traditional general-purpose FPGA devices, especially if characteristics of a target application domain are known a priori.

关键词： field programmable gate arrays

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Automatic transistor and physical design of FPGA tiles from an architectural specification

Automatic transistor and physical design of FPGA tiles from ...

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Padalia, Ketan Fung, Ryan Bourgeault, Mark Egier, Aaron Rose, Jonathan Edward S. Rogers Sr. Dept. of ECE University of Toronto Toronto Ont. M5S 3G4 Canada

One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywhere from 50 to 200 man-years simply in the layout step. To date, automated tools have only been employed in small parts of the periphery and programming circuitry. The core tiles, which are repeated many times, are subject to painstaking manual design and layout. In this paper we present a new system (called GILES, for Good Instant Layout of Erasable Semiconductors) that automatically generates a transistor-level schematic from a high-level architectural specification of an FPGA. It also generates a cell-level netlist that is placed and routed automatically. The architectural specification is the one used as input to the VPR [3] architectural exploration tool. The output is the mask-level layout of a single tile that can be replicated to form an FPGA array. We describe a new placement tool that simultaneously places and compacts the layout to minimize white space and wiring demand, and a special-purpose router built for this task. GILES can place and route a tile consisting of four 4-input LUT logic cells and all of its programmable wires in a 0.18 μm CMOS process using 8 layers of metal and 25983 μm2 of area. When we generate the layout of an architecture similar to-the Xilinx Virtex-E FPGA (built in a 0.1 μm process) GILES requires only 47% more area than the original. The layout area of an architecture similar to the Altera Apex 20K400E (also built in a 0.18 μm process) constructed by GILES requires 97% more area than the original.

关键词： field programmable gate arrays

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An architectural exploration of via patterned gate arrays 03

An architectural exploration of via patterned gate arrays

引用

2003 international symposium on Physical Design

作者： Patel, Chetan Cozzie, Anthony Schmit, Herman Pileggi, Larry Carnegie Mellon University 5000 Forbes Ave Pittsburgh PA 15213 United States

ISBN: (纸本)9781581136500

In this work we investigate the architecture of a Via Patterned gate Array (VPGA) [1], focusing primarily on: 1) the optimal lookup table (LUT) size;and 2) a comparison the crossbar and switch block routing architectures. Unlike FPGAs, the routing architectures in a VPGA do not dominate the total area of the circuit. Therefore our results suggest that using smaller LUTs results in a much faster and smaller design. In the routing architecture comparison, our results also show that the switch block architecture is inferior to the crossbar architecture in terms of area utilization. As the number of routing tracks grows, the switch block architecture begins to dominate the total area of the design as in the case of the FPGAs.

关键词： field programmable gate arrays

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