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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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A run-time reconfigurable system for gene-sequence searching 16

A run-time reconfigurable system for gene-sequence searching

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16th international Conference on VLSI Design/2nd international Conference on Embedded Systems Design

作者： Puttegowda, K Worek, W Pappas, N Dandapani, A Athanas, P Dickerman, A Virginia Polytech Inst & State Univ Blacksburg VA 24061 USA

ISBN: (纸本)0769518680

Advances in the field of bio-technology has led to an ever increasing demand for computational resources to rapidly search large databases of genetic information. Databases with billions of data elements are routinely compared: and searched for matching and near-matching patterns. In this paper we present a system developed to search DNA sequence data using run-time reconfiguration of field programmable gate arrays (FPGAs). The system provides an order of magnitude increase in performance while reducing hardware complexity when compared to existing commercial systems.

关键词： Bioinformatics Costs Databases DNA field programmable gate arraysvGenetics Hardware Proteins Runtime Sequences

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A custom FPGA for the simulation of gene regulatory networks

A custom FPGA for the simulation of gene regulatory networks

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proceedings of the 2003 acm Great Lakes symposium on VLSI

作者： Tagkopoulos, Ilias Zukowski, Charles Cavelier, German Anastassiou, Dimitris Department of Electrical Engineering Columbia University 500 W. 120th Street New York NY 10027 United States

We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4×5 array of configurable logic blocks along with programmable interconnect. It can simulate a network of pathways involving up to 20 genes and their associated proteins. The circuit design takes advantage of a number of analogies between CMOS circuits and gene networks. For example, a capacitor charge is used to represent a protein concentration, currents represent protein production, and a transistor switch network is used to compute the influences of activator and repressor proteins on gene expression. A simulation shows how the chip can predict oscillatory behavior in a particular well-known three-gene system.

关键词： field programmable gate arrays

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A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology 03

A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS te...

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proceedings of the 2003 acm Great Lakes symposium on VLSI

作者： You, Chao Guo, Jong-Ru Kraft, Russell P. Zhou, Kuan Chu, Michael McDonald, John F. Rensselaer Polytechnic Institute 110 8th St Troy NY 12180 United States

ISBN: (纸本)9781581136777

A high speed, low power FPGA design is presented in this paper. This gigahertz FPGA design has an improved XC6200 structure. Redundant multiplexers are eliminated from critical signal path to enhance the performance of the previous design. By balancing between the power consumption and performance, the simulated clock rate is from 5 GHz to 20 GHz and the power consumption is from 4 mW to 12 mW per single cell in the IBM 7HP SiGe HBT BiCMOS process.

关键词： field programmable gate arrays

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Comparison of heuristic algorithms for variable partitioning in circuit implementation 16

Comparison of heuristic algorithms for variable partitioning...

引用

16th international Conference on VLSI Design/2nd international Conference on Embedded Systems Design

作者： Muthukumar, V Selvaraj, H Univ Nevada Dept Elect & Comp Engn Las Vegas NV 89154 USA

ISBN: (纸本)0769518680

Functional decomposition is a process of splitting a complex circuit into smaller sub-circuits. This paper deals with the problem of determining the set of best free and bound variables (variable partitioning problem) for disjoint (disjoint serial) decomposition, such that the decomposed circuits are smaller in size and its truth table representation have maximal don't cares. A novel pruned breadth first search (PBFS/IPBFS) approach is proposed to determine the set of good variable partitions with minimal time and computational complexity. The heuristics proposed minimize the size of the sub-functions. The proposed approach has been successfully implemented and test with MCNC and Espresso benchmarks.

关键词： Benchmark testing Circuit synthesis Circuit testing Computational complexity Cost function field programmable gate arrays Heuristic algorithms Input variables Partitioning algorithms Search methods

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Low power technology mapping for LUT based FPGA - A genetic algorithm approach 16

Low power technology mapping for LUT based FPGA - A genetic ...

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16th international Conference on VLSI Design/2nd international Conference on Embedded Systems Design

作者： Pandey, R Chattopadhyay, S Indian Inst Technol Dept Comp Sci & Engn Gauhati India

ISBN: (纸本)0769518680

In this paper we consider the problem of LookUp Table(LUT) based FPGA technology mapping for power minimization in combinational circuits. The problem has been previously proven to be NP-complete and here we present an efficient Genetic Algorithm solution for it. Considering that the connection switches posses large resistance and capacitance in LUT based FPGA, the fitness of the chromosome is selected based on its ability to reduce the transition probability on "visible" edges of mapped logic circuits by hiding the paths with high transition activity in the "invisible" edges. Meanwhile, the number of LUT is also kept small.

关键词： Biological cells Capacitance Combinational circuits field programmable gate arrays Genetic algorithms Logic circuits Minimization Switches Switching circuits Table lookup

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Zero overhead watermarking technique for FPGA designs

Zero overhead watermarking technique for FPGA designs

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proceedings of the 2003 acm Great Lakes symposium on VLSI

作者： Jain, Adarsh K. Yuan, Lin Pari, Pushkin R. Qu, Gang Department of Electrical Engineering University of Maryland College Park MD United States

FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing watermarking and fingerprinting techniques successfully embed identification information into FPGA designs to deter IP infringement. However, such methods incur timing and/or resource overhead, unpredictable at times, which causes performance degradation. In this paper, we propose a new FPGA watermarking technique that guarantees zero design overhead. Our approach consists of two phases. First we design as usual to obtain the best, possible, quality IP. Then we map the required signature to additional timing constraints on carefully selected nets and redo a small portion of the design (e.g. place and route). The FPGA configuration bitstream for the resulting watermarked design will be significantly different from the original design, which provides us with a strong proof of authorship. The watermarking technique has zero design overhead because it is developed to maintain the performance of the design from the first phase. This is demonstrated by applying the proposed technique on several real-life FPGA designs, which range in size from a few thousand to more than two million gates, on Xilinx devices.

关键词： field programmable gate arrays

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Task graph extraction for embedded system synthesis 16

Task graph extraction for embedded system synthesis

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16th international Conference on VLSI Design/2nd international Conference on Embedded Systems Design

作者： Vallerio, KS Jha, NK Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)0769518680

Consumer demand and improvements in hardware have caused distributed real-time embedded systems to rapidly increase in complexity. As a result, designers faced with time-to-market constraints are forced to rely on intelligent design tools to enable them to keep up with demand These tools are continually being used earlier in the design process when the design is at higher levels of abstraction. At the highest level of abstraction are hardware/software co-synthesis tools which take a system specification as input. Although many embedded systems are described in C, the system specifications for many of these tools are often in the form of one or more task graphs. These tools are very effective at solving the co-synthesis problem using task graphs but require that designers manually transform the specification from C code to task graphs, a tedious and error-prone job. The task graph extraction tool described in this paper reduces the potential for error and the time required to design an embedded system by automating the task graph extraction process. Such a tool can drastically improve designer productivity. As far as we know, this is the first tool of its kind. It has been made available on the web.

关键词： Embedded software Embedded system field programmable gate arrays Hardware Job design Process design Productivity Real time systems Software libraries Software tools

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Panel: Attack of the killer gate arrays 03

Panel: Attack of the killer gate arrays

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proceedings of the 2003 acm/sigda eleventh international symposium on field programmable gate arrays

作者： Michael Butts Jonathan Rose Steve Trimberger Herman Schmit Cadence Altera Xilinx CMU

ISBN: (纸本)9781581136517

The ever-growing capacity and speed of FPGAs have brought them into the heart of the silicon mainstream. Major ASIC vendors have responded by reviving masterslice gate arrays, standard prefab die with design-specific metal layers. They claim lower NREs, quicker delivery and easier design than cell-based ASICs, and lower unit cost, better speed, capacity and power than *** these gate arrays spell doom for FPGA vendors' dreams of displacing the ASIC as a mainstream silicon platform?Will the FPGA's high volume, superior flexibility and time-to-market prevail?Will FPGA's co-exist in different classes of application?A panel of experts from FPGA and ASIC vendors and academia will duke it out. Each panelist will give a short presentation putting forward their point of view followed by an interactive debate among the panelists and attendees.

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Future design tools for platform FPGAs 03

Future design tools for platform FPGAs

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symposium on Integrated Circuits and Systems Design (SBCCI)

作者： P. Lysaght Xilinx Research Laboratories CA USA

ISBN: (纸本)9780769520094

According to current projections, programmable platforms will dominate ASIC design starts as the semiconductor industry moves to 90 nm process technology and beyond. In this paper, we assess the implications of this trend and explore the impact it will have on system-level design methodologies for FPGAs. We review current research and practice in system-level design and attempt to assess how much of the ASIC experience will be relevant to future FPGA designers.

关键词： field programmable gate arrays Application specific integrated circuits System-level design Concurrent computing Electronics industry Costs Digital signal processing Embedded software Logic design Silicon

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ReCoNet: modeling and implementation of fault tolerant distributed reconfigurable hardware 03

ReCoNet: modeling and implementation of fault tolerant distr...

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symposium on Integrated Circuits and Systems Design (SBCCI)

作者： C. Haubelt D. Koch J. Teich Department of Computer Science 12 University of Erlangen Nuremberg Germany

ISBN: (纸本)9780769520094

Recent research was mainly focused on the OS support for a single reconfigurable chip. This paper presents a general approach to manage fault tolerant distributed reconfigurable hardware. In order to run such a system, three basic tasks must be implemented: (i) rerouting to compensate line errors, (ii) rebinding to compensate node failures, and (iii) hardware reconfiguration to allow the optimization of these systems during runtime. This paper proposes first ideas and solutions of these management functions. Furthermore, a prototype implementation consisting of four fully connected FPGAs is presented.

关键词： Fault tolerance Hardware field programmable gate arrays Prototypes Energy consumption Delay Computer science Operating systems Automotive engineering Body area networks

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