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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 834 条记录，以下是621-630 订阅

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FPGA implementation of neighborhood-of-four cellular automata random number generators 02

FPGA implementation of neighborhood-of-four cellular automat...

引用

FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Shackleford, Barry Tanaka, Motoo Carter, Richard J. Snider, Greg Hewlett-Packard Laboratories 1501 Page Mill Rd. Palo Alto CA 94304 United States

ISBN: (纸本)9781581134520

Random number generators (RNGs) based upon neighborhood-of-four cellular automata (CA) with asymmetrical, non-local connections are explored. A number of RNGs that pass Marsaglia's rigorous Diehard suite of random number tests have been discovered. A neighborhood size of four allows a single CA cell to be implemented with a four-input lookup table and a one-bit register which are common building blocks in popular field programmable gate arrays (FPGAs). The investigated networks all had periodic (wrap around) boundary conditions with either 1-d, 2-d, or 3-d interconnection topologies. Trial designs of 64-bit networks using a Xilinx XCV 1000-6 FPGA predict a maximum clock rate of 214 MHz to 230 MHz depending upon interconnection topology.

关键词： field programmable gate arrays

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Data reorganization engines for the next generation of system-on-a-chip FPGAs 02

Data reorganization engines for the next generation of syste...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Diniz, Pedro C. Park, Joonseok University of Southern California Information Sciences Institute 4676 Admiralty Way Marina del Rey CA 90292 United States

ISBN: (纸本)9781581134520

field-programmable-Core-arrays (FPCA) will include various computing cores for a wide variety of applications ranging from DSP to general purpose computing. With the increasing gap between core computing speeds and memory access latency, managing and orchestrating the movement of data across multiple cores will become increasingly important. In this paper we propose data reorganization engines that allow a wide variety of data reorganizations intra- as well as inter-memory modules for future FPCAs. We have experimented with a suite of data reorganizations pervasive in DSP applications. Our limited set of experiments reveals that the proposed designs for these engines are flexile and use little design area in current FPGA fabrics, making them amenable to be easily integrated in future FPCAs as either soft- or hard- macros.

关键词： field programmable gate arrays

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Dynamic power consumption in virtex™-II FPGA family 02

Dynamic power consumption in virtex™-II FPGA family

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Shang, Li Kaviani, Alireza S. Bathala, Kusuma Princeton University EE Dept. Princeton NJ 08540 United States

ISBN: (纸本)9781581134520

This paper analyzes the dynamic power consumption in the fabric of field programmable gate arrays (FPGAs) by taking advantage of both simulation and measurement. Our target device is Xilinx Virtex™-II family, which contains the most recent and largest programmable fabric. We identify important resources in the FPGA architecture and obtain their utilization, using a large set Of real designs. Then, using a number of representative case studies we calculate the switching activity corresponding to each resource. Finally, we combine effective capacitance of each resource with its utilization and switching activity to estimate its share of power consumption. According to our results, the power dissipation share of routing, logic and clocking resources are 60%, 16%, and 14%, respectively. Also, we concluded that dynamic power dissipation of a Virtex-II CLB is 5.9 μW per MHz for typical designs, but it may vary significantly depending on the switching activity.

关键词： field programmable gate arrays

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Cryptographic rights management of FPGA intellectual property cores

Cryptographic rights management of FPGA intellectual propert...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Kean, Tom Algotronix Ltd. PO Box 23116 Edinburgh EH8 8YB United Kingdom

As the capacity of FPGA's increases to millions of equivalent gates the use of Intellectual Property (IP) cores becomes increasingly important to control design complexity. FPGA's are becoming platforms for integrating a system solution from components supplied by independent vendors in the same way as printed circuit boards provided a platform for earlier generations of designers. However, the current commercial model for IP cores involves large up-front license fees reminiscent of ASIC NRE charges. In order to match the IP core business model to the low to medium volume applications addressed by FPGA customers it is important to develop cryptographic techniques which allow IP core vendors to sell their product on a pay-per-use basis rather than through up-front license fees.

关键词： field programmable gate arrays

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FPGA switch block layout and evaluation 02

FPGA switch block layout and evaluation

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Schmit, Herman Chandra, Vikas Department of ECE Carnegie Mellon University Pittsburgh PA 15213 United States

ISBN: (纸本)9781581134520

This paper presents abstract layout techniques for a variety of FPGA switch block architectures. We evaluate the relative density of subset, universal, and Wilton switch block architectures. For subset switch blocks of small size, we find the optimal implementations using a simple metric. We also develop a tractable heuristic that returns the optimal results for small switch blocks, and good results for large switch blocks. For switch blocks with general connectivity, we develop a representation and a layout evaluation technique. We use these techniques to compare a variety of small switch blocks. We find that the traditional Xilinx-style, subset switch block is superior to the other proposed architectures. Finally, we have hand-designed some small switch blocks to confirm our results.

关键词： field programmable gate arrays

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Efficient circuit clustering for area and power reduction in FPGAs 02

Efficient circuit clustering for area and power reduction in...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Singh, Amit Marek-Sadowska, Malgorzata Department of Elec. and Comp. Eng. Univ. of California Santa Barbara Santa Barbara CA 93106 United States

ISBN: (纸本)9781581134520

We present a routability-driven bottom-up clustering technique for area and power reduction in clustered FPGAs. This technique uses a cell connectivity metric to identify seeds for efficient clustering. Effective seed selection, coupled with an interconnect-resource aware clustering and placement, can have a favorable impact on circuit routability. It leads to better device utilization, savings in area, and reduction in power consumption. Routing area reduction of 35% is achieved over previously published results. Power dissipation simulations using a buffered pass-transistor-based FPGA interconnect model are presented. They show that our clustering technique can reduce the overall device power dissipation by an average of 13%.

关键词： field programmable gate arrays

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A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs 02

A flexible floating-point format for optimizing data-paths a...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Dido, J. Geraudie, N. Loiseau, L. Payeur, O. Savaria, Y. Poirier, D. Microelectronics Research Group Ecole Polytechnique of Montreal CP 6079 Succ. Centre Ville Montréal Que. H3C 3A7 Canada

ISBN: (纸本)9781581134520

Video signal processing requires complex algorithms performing many basic operations on a video stream. To perform these calculations in real-time in a FPGA, we must use innovative structures to meet speed requirements while managing complexity. As part of a project aiming at the development of a video noise reducer, we developed an optimized processing stream that required some floating-point calculations. This paper presents the rationale for developing a floating-point unit, justifies the data representation used, its implementation in a Xilinx VirtexE FPGA and reports the performance we obtained. A divider using this representation is also presented, with its implementation and performances in the same FPGA.

关键词： field programmable gate arrays

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Circuit design of routing switches 02

Circuit design of routing switches

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Lemieux, Guy Lewis, David Dept. of Electrical and Comp. Eng. University of Toronto Toronto Ont. M5S 3G4 Canada

ISBN: (纸本)9781581134520

This paper examines circuit design of buffered routing switches in symmetrical, island-style FPGAs. The effects of switch size, tile length, level-restoring, and slow input slew rates are examined. Two new fanin-based switch designs are used to eliminate nearly all of the increase in delay that arises from fanout with a previous switch design. Alternating between buffers and pass transistors is shown to improve connection delay without fanout by 25 %. To take advantage of this, we propose schemes to replace some buffers with pass transistors to simultaneously reduce area and delay. Routing a suite of MCNC benchmark circuits shows that 14% in areadelay, or 7% in delay can be saved using the new switch schemes. Alternatively, approximately 13 % in area can be saved with no degradation to delay.

关键词： field programmable gate arrays

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On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques 02

On the sensitivity of FPGA architectural conclusions to expe...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Yan, Andy Cheng, Rebecca Wilton, Steven J.E. Dept. of Elec. and Computer Eng. University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781581134520

Recent years have seen a tremendous increase in the capacities and capabilities of field-programmable gate arrays (FPGA's). Much of this dramatic improvement has been the result of changes to the FPGAs' internal architectures. New architectural proposals are routinely generated in both academia and industry. For FPGA's to continue to grow, it is important that these new architectural ideas are fairly and accurately evaluated, so that those worthy ideas can be included in future chips. Typically, this evaluation is done using experimentation. However, the use of experimentation is dangerous, since it requires making assumptions regarding the tools and architecture of the device in question. If these assumptions are not accurate, the conclusions from the experiments may not be meaningful. In this paper, we investigate the sensitivity of FPGA architectural conclusions to experimental variations. To make our study concrete, we evaluate the sensitivity of four previously published and well-known FPGA architectural results: lookup-table size, switch block topology, cluster size, and memory size. It is shown that these experiments are significantly affected by the assumptions, tools, and techniques used in the experiments.

关键词： field programmable gate arrays

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Reliable laser programmable gate array technology 3

引用

3rd international symposium on Quality Electronic Design

作者： Gao, Z Luo, J Huang, H Zhang, W Bernstein, JB Univ Maryland College Pk MD 20742 USA

ISBN: (纸本)0769515622

field-programmable gate arrays have become popular ever since their introduction. Compared to other digital circuit implementation media, they have lower NRE cost and rapid turnaround with the penalties of reduced speed and larger size. Thus better FPGA programmable switch technology is desired in order to gain speed and density advantages. In this paper, Laser-induced MakeLink(TM)* technology is proposed as a programmable switch element. The Electrical resistance is as low as 0.8 Omega to 11 Omega, depending on the size of the link, which is 2-3 orders smaller than that of NMOS transistor in a SRAM based FPGA. Thus the speed improvement for Laser field-programmable gate Array (LFPGA) is significant. Other features of Laser-induced vertical links technology, such as small size and radiation hardness, car, also greatly improve the FPGA performance. The cluster-based LFPGA with 128 by 64 basic logic elements (BLE) is laid out under a 0.5 mum commercialized technology. The chip size is about 138mm(2).

关键词： Costs Digital circuits Electric resistance field programmable gate arrays Logic MOSFETs Optical arrays Random access memory Reliability engineering Switches

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