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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine

Analysis of quasi-static scheduling techniques in a virtuali...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Markovskiy, Yury Caspi, Eylon Huang, Randy Yeh, Joseph Chu, Michael Wawrzynek, John DeHon, Andreá University of California Berkeley CA United States

The SCORE compute model uses fixed-size, virtual compute and memory pages connected by stream links to capture the definition of a computation abstracted from the detailed size of the physical hardware. When the number of physical compute pages is smaller than the number of virtual compute pages in the abstract computation graph, the design is time-multiplexed onto the available physical hardware. A key component of this strategy is an automatic scheduler that selects the temporal sequencing of virtual resources onto the physical device. We describe a quasi-static scheduling strategy that retains the full semantic power of the dynamic SCORE flow graph while taking advantage of static scheduling techniques at program load time to hoist most of the computational work out of the inner scheduling loops. This strategy reduces online scheduling work per reconfiguration epoch by an order of magnitude. In addition, a more global perspective available from offline-scheduling improves schedule quality, resulting in a net reduction of total execution time by 46-81%.

关键词： field programmable gate arrays

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A faster distributed arithmetic architecture for FPGAs 02

A faster distributed arithmetic architecture for FPGAs

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Grover, Radhika S. Shang, Weijia Li, Qiang Department of Computer Engineering Santa Clara University Santa Clara CA United States

ISBN: (纸本)9781581134520

Distributed Arithmetic (DA) is an important technique to implement digital signal processing (DSP) functions in FPGAs. However, traditional lookup table (LUT) based DA architectures contain one or more carry propagation chains in the critical path that dictates the fastest time at which an entire design can run. In this paper, we describe a novel technique that can reduce or eliminate the carry-propagate chain from the critical path in LUT based DA architectures on FPGAs. In the proposed scheme, the individual bits of a word do not have to be processed as a unit. Instead, the current iteration can start as soon as the least significant bit (LSB) of the previous iteration is available, without waiting for the entire word from the previous iteration to be fully computed. This technique has great potential in speeding up DSP applications based on DA. Designs are described for serial and parallel DALUT and accumulator structures in which an n-bit carry chain, where n is the word length, is broken into smaller r-bit chains, 1 ≤ r

关键词： field programmable gate arrays

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Timing verification of dynamically reconfigurable logic for the Xilinx Virtex FPGA series 02

Timing verification of dynamically reconfigurable logic for ...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Robertson, Ian Irvine, James Lysaght, Patrick Robinson, David Dept. Electronic and Electrical Eng. University of Strathclyde 204 George Street Glasgow G1 1XW United Kingdom

ISBN: (纸本)9781581134520

This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized.

关键词： field programmable gate arrays

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Application of FPGA technology to accelerate the Finite-Difference Time-Domain (FDTD) method 02

Application of FPGA technology to accelerate the Finite-Diff...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Schneider, Ryan N. Turner, Laurence E. Okoniewski, Michal M. University of Calgary Canada 2500 University Drive NW Calgary Alta. T2N 1N4 Canada

ISBN: (纸本)9781581134520

The continuing advances in the field of electrical engineering, in areas like cellular communications, fiber optics, mobile and multi-gigahertz electronics have necessitated a computer-assisted design approach to the complex electromagnetic interactions and problems that arise. Finite-Difference Time-Domain (FDTD) Analysis is a very powerful tool for the modeling of electromagnetic phenomena. The algorithm is computationally intensive and simulations can run for a few hours to several days. Increasing the computation speed and decreasing the run times of this algorithm would bring greater productivity and new avenues of research to many facets of electrical engineering. The algorithm is transferred to custom FPGA-based hardware using a pipelined bit-serial arithmetic architecture. A one-dimensional resonator is used to verify the implementation and explore the hardware speed and costs. The computational speed is extremely fast and is not related to the number of computational cells in the simulation. Finally, a discussion of future research is presented.

关键词： field programmable gate arrays

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Incremental reconfiguration of multi-FPGA systems 02

Incremental reconfiguration of multi-FPGA systems

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Lee, K.K. Wong, D.F. Synopsys Inc. Mountain View CA United States

ISBN: (纸本)9781581134520

In reconfigurable computing, circuits implemented on multi-FPGA systems have to be incrementally modified. Since reconfiguring an FPGA is time-consuming, the time for reconfiguration depends on the number of FPGAs to be reconfigured. Our objective is to reduce the number of such FPGAs. In this paper, we consider the specific problem of incrementally reconfiguring a multi-FPGA system that utilizes the direct interconnection architecture, where routing connections between FPGAs are to neighbors that are near. This problem can be divided into a net addition problem and a net deletion problem. We show that the net addition problem is a generalization of the NP-complete Steiner tree problem. Our algorithm for this problem is based on an adaptation of the Klein-Ravi approximation algorithm for the node-weighted Steiner tree problem. As for the net deletion problem, we prove that it is NP-complete but the problem is solvable in polynomial time for tree topologies. Based on the algorithm for trees, we design an effective heuristic algorithm for the general net deletion problem. Finally, we present an algorithm for solving the incremental reconfiguration problem which handles both placement of new gates and inter-FPGA routing.

关键词： field programmable gate arrays

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Integrated retiming and placement for field programmable gate arrays 02

Integrated retiming and placement for field programmable gat...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Singh, Deshanand P. Brown, Stephen D. Dept. of Elec. and Computer Eng. University of Toronto Toronto Ont. Canada

ISBN: (纸本)9781581134520

Retiming is a synchronous circuit transformation that can optimize the delay of a synchronous circuit by moving registers across combinational circuit elements. The combinational structure remains unchanged and the observable behavior of the circuit is identical to the original. In this paper, we address the problem of applying retiming techniques to circuits implemented in field programmable gate arrays (FPGAs). FPGAs contain prefabricated and configurable routing elements that allow us to easily implement a variety of circuits. However this interconnect contributes greatly to the overall delay in the implemented circuit. If a circuit is retimed prior to the placement and routing phases of the CAD flow, then it has no information about the delays introduced by the configurable interconnect. Our fundamental experiment is to determine whether there are any gains in tightly coupling retiming and placement so that the retiming algorithm has some estimate of the routing delays. Specifically, we introduce a post-placement retiming algorithm that understands how to take advantage of FPGA architectural features. This retiming algorithm may introduce extra registers into the circuit. These new registers need to be placed in some location in the FPGA. Retiming register placement is accomplished by a novel incremental clustering and placement algorithm. The incremental algorithm builds upon the placement of the non-retimed circuit to intelligently sift in the newly-introduced registers. In addition, we explore making the placement algorithms "retiming aware." These placement algorithms try to place logic blocks in such a way that the subsequent retiming produces better speed results. These techniques include the identification of retiming-critical cycles during placement. Our experiments show that the integration of retiming with placement results in 19% better clock periods in comparison to the application of retiming before the place and route steps.

关键词： field programmable gate arrays

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Parallel-beam backprojection: An FPGA implementation optimized for medical imaging 02

Parallel-beam backprojection: An FPGA implementation optimiz...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Coric, Srdjan Leeser, Miriam Miller, Eric Trepanier, Marc Dept. of Elec. and Comp. Engineering Northeastern University Boston MA 02115 United States

ISBN: (纸本)9781581134520

Medical image processing in general and computerized tomography (CT) in particular can benefit greatly from hardware acceleration. This application domain is marked by computationally intensive algorithms requiring the rapid processing of large amounts of data. To date, reconfigurable hardware has not been applied to this important area. For efficient implementation and maximum speedup, fixed-point implementations are required. The associated quantization errors must be carefully balanced against the requirements of the medical community. Specifically, care must be taken so that very little error is introduced compared to floating-point implementations and the visual quality of the images is not compromised. In this paper, we present an FPGA implementation of the parallel-beam backprojection algorithm used in CT for which all of these requirements are met. We explore a number of quantization issues arising in backprojection and concentrate on minimizing error while maximizing efficiency. Our implementation shows significant speedup over software versions of the same algorithm, and is more flexible than an ASIC implementation. Our FPGA implementation can easily be adapted to both medical sensors with different dynamic ranges as well as tomographic scanners employed in a wider range of application areas including nondestructive evaluation and baggage inspection in airport terminals.

关键词： field programmable gate arrays

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EVE: A CAD tool for manual placement and pipelining assistance of FPGA circuits 02

EVE: A CAD tool for manual placement and pipelining assistan...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Chow, William Rose, Jonathan Edward S. Rogers Sr. Dept. of ECE University of Toronto Toronto Ont. M5S 3G4 Canada

ISBN: (纸本)9781581134520

As FPGAs push ever deeper into mainstream digital design, there is an increasing desire for high-performance circuits. This paper describes a manual editor, called EVE, which can assist a designer to perform manual packing, placement and pipelining of commercial FPGA circuits to achieve a meaningful increase in performance. This effort is inspired by Von Herzen's paper, which proposed the notion of an "Event Horizon" - a high-speed circuit design approach in which complete knowledge of the timing effect of every synthesis change is used. It is very laborious to implement circuits using this approach;therefore we try to augment manual design tools in order to make this Event Horizon methodology easier to perform. This paper describes a first step in that direction, which focuses on placement, packing and pipelining. EVE provides an interactive environment that immediately reroutes and timing analyzes after each user circuit modification, giving an exact value for critical path delay. It can also suggest good placement positions and provide flip-flop insertion assist during pipelining. Compared to a state-of-the-art Synthesis and place and route flow, we used EVE to achieve an average of 12.7% higher operating frequency on a set of eight Xilinx Virtex-E circuits of 250 or fewer LUTs.

关键词： field programmable gate arrays

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Temporal logic replication for dynamically reconfigurable FPGA partitioning

Temporal logic replication for dynamically reconfigurable FP...

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ISPD-2002: international symposium on Physical Design

作者： Mak, Wai-Kei Young, Evangeline F.Y. Dept. of Computer Science and Eng. University of South Florida Tampa FL 33620-5399 United States

In this paper, we propose the idea of temporal logic replication in dynamically reconfigurable field-programmable gate array partitioning to reduce communication cost. Temporal logic replication has never been explored before. We define the min-area min-cut replication problem given a k-stage temporal partition satisfying all temporal constraints and devise an optimal algorithm to solve this problem. We have also devised a flow-based replication heuristic in case there is a tight area bound that limits the amount of replication. In addition, we will present a correct network flow model for partitioning sequential circuits temporally.

关键词： field programmable gate arrays

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Constrained Clock Shifting for field programmable gate arrays

Constrained Clock Shifting for field programmable gate array...

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FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Singh, Deshanand P. Brown, Stephen D. Dept. of Electrical and Comp. Eng. University of Toronto Toronto Ont. Canada

Circuits implemented in FPGAs have delays that are dominated by its programmable interconnect. This interconnect provides the ability to implement arbitrary connections. However, it contains both highly capacitive and resistive elements. The delay encountered by any connection depends strongly on the number of interconnect elements used to route the connection. These delays are only completely known after the place and route phase of the CAD flow. We propose the use of Clock Shifting optimization techniques to improve the clock frequency as a post place and route step. Clock Shifting Optimization is a technique first formalized in [4]. It is a cycle-stealing algorithm that allows one to reduce the critical path delay of a synchronous circuit by shifting the clock signals at each register. This technique allows late arriving signals to be sampled at a later point in time by intentionally introducing a skew on the clock input of the sampling register. Typical FPGAs contain a number of special purpose global clock networks that distribute clock signals to every register in the chip. Unused global clock lines in FPGAs can be used to distribute a finite set of clock skews to the entire circuit. We propose an efficient integer programming method to find the optimal circuit improvement for a finite set of clock skews. This technique is modified to consider inherent uncertainties present in the timing models. The uncertainty controls the aggressiveness of the optimizations as we must take great care in ensuring functionality for any range of possible timing characteristics. Our results confirm intuition that more aggressive speed optimizations can be performed as timing models become more accurate. We also show that providing 4 skewed versions of the nominal clock signal results in the best delay-area tradeoff. This result is evocative as it may suggest future FPGA architectures that contain greater numbers of global clock lines, as we tradeoff gains in speed for greater po

关键词： field programmable gate arrays

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