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Extending the Moore's law by exploring new data center architecture: Invited Paper 16

Extending the Moore's law by exploring new data center archi...

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21st IEEE/acm international symposium on Low Power Electronics and Design, ISLPED 2016

作者： Ouyang, Jian Qi, Wei Wang, Yong Baidu Baidu Campus Beijing China

ISBN: (纸本)9781450341851

In recent ten years, lots of new applications emerged, such as AI, big data and cloud. Though the workloads of these applications are very diverse, they demand huge resource of data center. In contrast, the silicon technology moves slower and slower because the Moore's law is going to the end. Consequently, the data center building from commodity hardware cannot provide enough costefficiency and power-efficiency. To meet the increasingly resource needs of emerging applications, the scale of data center is become much larger and larger. It consumes huge power and cost of hardware. From the business perspective, the slow development of hardware technology limits the value creation of emerging applications. We, Baidu, the largest search engine in China, have faced this challenge in several years ago. We find that the server number increases much faster than the scale of business. And this case is common for internet companies. Because the iteration of general processor becomes slower and slower. For example, Intel announced that the Tick-Tock production strategic was out of date in this early year. This problem drive us to look for new methods to boost business. From Internet Company's perspective, building new chips or new architecture based on its applications' characteristics makes sense. This method can break the limitation of commodity chips and commodity hardware. And according to academic and industry experiences, domain-specified architecture can achieve much better performance and power efficiency than general architecture. Consequently, we are exploring new architecture to extend Moore's law. In this paper, we present the works on exploring new architecture for data center. The data center resource includes storage, memory, computing and networking. Hence, we focus on these four areas. Firstly, we implemented SDF for large-scale distributed storage system. The SDF aims to low cost and high performance flash storage system. Secondly, we implemented SDA for dee

关键词： field programmable gate arrays (FPGA)

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Parameterizable floating-point library for arithmetic operations in FPGAs 09

Parameterizable floating-point library for arithmetic operat...

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22nd symposium on Integrated Circuits and Systems Design, SBCCI 2009

作者： Sánchez, Diego F. Muñoz, Daniel M. Llanos, Carlos H. Ayala-Rincón, Mauricio Pós-Graduação em Sistemas Mecatrônicos Engenharia Mecânica Universidade de Brasília 70910-900 Brasília D.F. Brazil Instituto de Ciências Exatas Universidade de Brasília 70910-900 Brasília D.F. Brazil

ISBN: (纸本)9781605587059

Floating-point operations are an essential requisite in a wide range of computational and engineering applications that need good performance and high precision. Current advances in VLSI technology raised the density integration fast enough, allowing the designers to develop directly in hardware several floating-point operations commonly implemented in software. Until now, most of the research has not focused on the tradeoff among the need of high performance and the cost of the size of logic area, associated with the level of precision, parameters that are very important in a wide variety of applications such as robotics, image and digital signal processing. This paper describes an FPGA implementation of a parameterizable floating-point library for addition/subtraction, multiplication, division and square root operations. Architectures based on Goldschmidt algorithm were implemented for computing floating-point division and square root. The library is parameterizable by bit-width and number of iterations. An analysis of the mean square error and the cost in area consumption is done in order to find, for general purpose applications, the feasible bit-width representation, number of iterations and number of addressable words for storing initial seeds of the Goldschmidt algorithm. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator 8

Enhanced use of mixed-mode clock manager for coherent sampli...

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8th international symposium on Computing and Networking Workshops, CANDARW 2020

作者： Fujieda, Naoki Takashima, Sogo Aichi Institute of Technology Faculty of Engineering Department of Electrical and Electronics Engineering Aichi Toyota Japan

ISBN: (纸本)9781728199191

A True Random Number Generator (TRNG) using a pair of Phase-locked Loops (PLLs) or Digital Clock Managers (DCMs) has an advantage of minimal usage of logic elements of FPGA. This paper focuses on a new clocking element of Xilinx FPGAs called mixed-mode clock manager (MMCM) and presents its effective use for better randomness and higher throughput. According to an evaluation on an Artix-7 FPGA using 132 sets of parameters, 89 sets passed AIS-31 Procedure B with the proposed method, while only 9 sets passed when simply porting an existing DCM-based method. The average throughput was 1.18 Mbit/s, which was 5x faster than an existing DCM-based method. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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Flexible FPGA Architecture realized of General Purpose SOG

Flexible FPGA Architecture realized of General Purpose SOG

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： K. Azegami S. Kashiwakura K. Yamashita Fujitsu Laboratories Limited Kawasaki Japan

In this paper, we describe an FPGA of high realization method flexibility, using general purpose SOG (sea of gates) gate array. Realization method flexibility means that we can realize the architecture by any method of realization, i.e. gate arrays and full customs. FPGAs determine their functions from their programmed internal state circuit. For example, SRAM program FPGAs do so by setting values to SRAMS. Our FPGA also uses SRAM program memory, but not limited. We will show one example of realization using general purpose SOG gate arrays. Our test SOG FPGA has a capacity of 6.5Kgate on a 14mm x 14mm die, with less than 2ns propagation delay between local logic cells.

关键词： field programmable gate arrays

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Accelerating machine learning kernel in hadoop using FPGAs 15

Accelerating machine learning kernel in hadoop using FPGAs

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15th IEEE/acm international symposium on Cluster, Cloud, and Grid Computing, CCGrid 2015

作者： Neshatpour, Katayoun Malik, Maria Homayoun, Houman Department of Electrical and Computer Engineering George Mason University United States

ISBN: (纸本)9781479980062

Big data applications share inherent characteristics that are fundamentally different from traditional desktop CPU, parallel and web service applications. They rely on deep machine learning and data mining applications. A recent trend for big data analytics is to provide heterogeneous architectures to allow support for hardware specialization to construct the right processing engine for analytics applications. However, these specialized heterogeneous architectures require extensive exploration of design aspects to find the optimal architecture in terms of performance and cost. % Considering the time dedicated to create such specialized architectures, a model that estimates the potential speedup achievable through offloading various parts of the algorithm to specialized hardware would be necessary. This paper analyzes how offloading computational intensive kernels of machine learning algorithms to a heterogeneous CPU+FPGA platform enhances the performance. We use the latest Xilinx Signboards for implementation and result analysis. Furthermore, we perform a comprehensive analysis of communication and computation overheads such as data I/O movements, and calling several standard libraries that can not be offloaded to the accelerator to understand how the speedup of each application will contribute to its overall execution in an end-to-end Hadoop MapReduce environment. © 2015 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Software-Defined mmWave Radio Architecture Comprised of Modular, Controllable Pixels to attain Near-Infinite Pattern, Polarization, and Beam Steering Angles IMS

A Software-Defined mmWave Radio Architecture Comprised of Mo...

引用

IEEE/MTT-S international Microwave symposium (IMS)

作者： Park, Junho Choi, Dongkwon Hong, Wonbin Pohang Univ Sci & Technol Pohang South Korea

ISBN: (纸本)9781728168159

This paper presents a software-defined mmWave radio architecture using modular/controllable antenna pixels for 5G/B5G beamforming systems. The operating mechanism of the proposed phased array is conceptually analogous to that of a field programmable gate array (FGPA) board. The proposed concept not only supports almost infinite radiation modes, but is fully compatible with the currently existing mmWave beamforming architecture. The proposed concept can be modularly expanded into a two-dimensional structure exemplified in the 4 x 4 array using a low temperature co-fired ceramic process. The proof-of-concept model features multiple polarizations with different beamsteering angle selected from 513 theoretically available modes.

关键词： millimeter-wave antennas 5G software-defined radio phased arrays reconfigurable antenna

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Computing the Discrete Fourier Transform on FPGA Based Systolic arrays

Computing the Discrete Fourier Transform on FPGA Based Systo...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： C. Dick School of Electronic Engineering La Trobe University Melbourne Australia

Reconfigurable logic arrays allow for the creation on the one physical hardware platform many different virtual circuits. A configuration bit-stream loaded into the logic array specifies the virtual circuit implemented. This paper addresses the problem of implementing FFTs using virtual computers based on Xilinx FPGAs. A systolic array processor architecture consisting of processing elements (PEs) employing CORDIC arithmetic is presented. The CORDIC approach removes the requirement for area consuming multipliers in the design. The method is suitable for handling power-of-2 and non power-of-2 transform lengths. The modular nature of the design provides for a highly scalable architecture that provides the system designer with a flexible mechanism for making cost-performance tradeoffs. The array processor and PE architecture are described. Based on simulation results, FPGA device utilization and transform execution time are calculated.

关键词： Discrete Fourier transforms field programmable gate arrays Systolic arrays Logic arrays Reconfigurable logic Hardware Logic circuits Flexible printed circuits Computer architecture Arithmetic

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Pinot:: Speculative multi-threading processor architecture exploiting parallelism over a wide range of granularities 38

<i>Pinot</i>:: Speculative multi-threading processor archite...

引用

38th Annual IEEE/acm international symposium on Microarchitecture

作者： Ohsawa, T Takagi, M Kawahara, S Matsushita, S NEC Corporation

ISBN: (纸本)0769524400

We propose a speculative multi-threading processor architecture called Pinot. Pinot exploits parallelism over a wide range of granularities without modifying program sources. Since exploitation of fine-grain parallelism suffers from limits of parallelism and overhead incurred by parallelization, it is better to extract coarse-grain parallelism. Coarse-grain parallelism is biased in some programs (mainly, numerical ones) and some program portions. Therefore, exploiting both coarsen and fine-grain parallelism is a key to the performance of speculative multithreading. The features of Pinot are as follows: (1) A parallelizing tool extracts parallelism at any level of granularity (e.g. even ten thousand instructions) from any program sub-structures (e.g. loops, calls, or basic blocks). The tool utilizes formulation in which the parallelization process is reduced to a combinatorial optimization problem. (2) A parallel execution model with extension of thread control instructions is designed in order to minimize the increase of the dynamic instruction count. The model employs implicit thread termination and cancellation, as well as register value transfer without synchronization. (3) A versioning cache called Version Resolution Cache (VRC) accomplishes both coarse- and fine-grained speculative multithreading. VRC operates as a large buffer for coarse-grained multi-threading. In addition, it provides low latency inter-thread communication with an update-based protocol for fine-grained multi-threading. We performed cycle-accurate simulations with 38 programs from the SPEC and MiBench benchmarks. The speedup with 4-processor-element-Pinot is up to 3.7 times, and 2.2 times on geometric mean against a conventional processor The speedup in a program (susan) drops from 3.7 to 1.6 when the speculative buffer size is limited to 256 bytes. It confirms that exploiting coarse-grain parallelism is essential to the improved performance. FPGA implementation shows 32% overhead of area and

关键词： Yarn Delay Multithreading National electric code Design optimization Termination of employment Frequency synchronization Protocols field programmable gate arrays Throughput

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Logic Partition Orderings for Multi-FPGA Systems

Logic Partition Orderings for Multi-FPGA Systems

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： S. Hauck G. Borriello Department of Computer Science and Engineering University of Washington Seattle WA USA

One of the critical issues for multi-FPGA systems is developing software tools for automatically mapping circuits. In this paper we consider one step in this process, partitioning. We describe the task of finding partition orderings, i.e., determining the way in which a circuit should be bipartitioned so as to best map it to a multi-FPGA system. This allows multi-FPGA partitioners to harness standard partitioning techniques. We develop an algorithm for finding partition orderings, which includes a method for increasing parallelism in the process, as well as for including multi-sectioning and multi-way partitioning algorithms. This method is very efficient, and capable of handling most of the current multi-FPGA topologies.

关键词： field programmable gate arrays Application specific integrated circuits Routing Partitioning algorithms Logic circuits Circuit simulation Computer science Software tools Parallel processing Circuit topology

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Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses

Synthesis of Signal Processing Structured Datapaths for FPGA...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： B. Haroun B. Sajjadi Department of Electrical and Computer Engineering Concordia University Montreal QUE Canada

A novel approach is presented for transforming a given scheduled and bound signal processing algorithm for a multiplexer based datapath to a BUS/RAM based FPGA datapath. A datapath model is introduced that allows maximum flexibility in scheduling bus transfers independent of operation scheduling. A novel integer linear programming (ILP) formulation that optimally selects and assigns data-transfers to busses while scheduling the bus transfers to minimize a linear combination of the number of busses, bus loading in terms of tristate drivers and fanout, registers and register file storage (RAM) locations. We demonstrate that our resulting optimal datapaths compare favorably to others for signal processing synthesis benchmarks such as: single and multiple elliptic filter and fast discrete-cosine-transform (FDCT).

关键词： Signal synthesis Signal processing field programmable gate arrays Registers Multiplexing Delay effects Logic Table lookup Signal processing algorithms Switches

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