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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Automatic Generation of Efficient Accelerators for Reconfigurable Hardware 16

Automatic Generation of Efficient Accelerators for Reconfigu...

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43rd acm/IEEE Annual international symposium on Computer Architecture (ISCA)

作者： Koeplinger, David Prabhakar, Raghu Zhang, Yaqi Delimitrou, Christina Kozyrakis, Christos Olukotun, Kunle Stanford Univ Stanford CA 94305 USA Cornell Univ Ithaca NY 14853 USA Ecole Polytech Fed Lausanne Lausanne Switzerland

ISBN: (纸本)9781467389471

Acceleration in the form of customized datapaths offer large performance and energy improvements over general purpose processors. Reconfigurable fabrics such as FPGAs are gaining popularity for use in implementing application-specific accelerators, thereby increasing the importance of having good high-level FPGA design tools. However, current tools for targeting FPGAs offer inadequate support for high-level programming, resource estimation, and rapid and automatic design space exploration. We describe a design framework that addresses these challenges. We introduce a new representation of hardware using parameterized templates that captures locality and parallelism information at multiple levels of nesting. This representation is designed to be automatically generated from high-level languages based on parallel patterns. We describe a hybrid area estimation technique which uses template-level models and design-level artificial neural networks to account for effects from hardware place-and-route tools, including routing overheads, register and block RAM duplication, and LUT packing. Our runtime estimation accounts for off-chip memory accesses. We use our estimation capabilities to rapidly explore a large space of designs across tile sizes, parallelization factors, and optional coarse-grained pipelining, all at multiple loop levels. We show that estimates average 4.8% error for logic resources, 6.1% error for runtimes, and are 279 to 6533 times faster than a commercial high-level synthesis tool. We compare the best-performing designs to optimized CPU code running on a server-grade 6 core processor and show speedups of up to 16.7x.

关键词： field programmable gate arrays Hardware Pipeline processing Space exploration Estimation Design tools

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Design and Implementation of a field programmable Analogue Array

Design and Implementation of a Field Programmable Analogue A...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： A. Bratt I. Macbeth Gadbrook Business Centre Pilkington Micro-Electronics Limited Northwich Cheshire UK

A field programmable Analogue Array (FPAA) is presented based on switched capacitor technology. The chip allows true array programming of undedicated analogue cells. There is provision for internal signal-conditional switching as part of the normal function of the array. With the presented chip it is possible to implement a very wide range of analogue signal processing functions such as data conversion, linear signal processing and non-linear functions. These functional configurations can be reconfigured and parameterised on the fly during concurrent signal processing. Very rapid prototyping of switched capacitor circuits is facilitated. The field programmable nature of the chip allows several markets/customers to be targeted simultaneously with obvious benefits in terms of both volume of sales and reduced time to market.

关键词： field programmable analog arrays Array signal processing Switched capacitor circuits Switches Integrated circuit interconnections Signal design Transfer functions Data conversion Prototypes Marketing and sales

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CASpEr: CAD framework for a novel transistor-level programmable fabric 52

CASpEr: CAD framework for a novel transistor-level programma...

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52nd IEEE international symposium on Circuits and Systems, ISCAS 2020

作者： Shihab, Mustafa M. Ramanidharan, Bharath Reddy, Gaurav Rajavendra Tian, Jingxian Swartz, William Sechen, Carl Makris, Yiorgos Department of Electrical and Computer Engineering The University of Texas at Dallas Richardson United States

ISBN: (纸本)9781728133201

A recently proposed TRAnsistor-level programmable (TRAP) fabric can enable seamless on-die integration of high-density reconfigurable logic with custom ICs. However, state-of-the-art CAD tools are developed for either ASICs or FPGAs and do not support the new architecture. To this end, we present CASPER - a novel CAD framework for implementing designs on the TRAP fabric. CASPER begins with characterizing an ASIC-esque cell library in order to leverage the industry-leading logic synthesis tools for TRAP. We then systematically remodel the TimberWolf and the Versatile Place and Route (VPR) tools to facilitate TRAP-specific design placement and routing, respectively. In addition, we develop a robust programming bitstream generation tool for TRAP. Lastly, we fabricate a 65nm prototype TRAP chip and implement ten ISCAS-85/MCNC benchmark circuits on it. Our evaluation results validate the proposed CAD framework and provide a comparative overhead analysis between TRAP and FPGA. © 2020 IEEE

关键词： field programmable gate arrays (FPGA)

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Towards a single event upset detector based on COTS FPGA

Towards a single event upset detector based on COTS FPGA

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2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and international symposium of System-on-Chip, SoC 2017

作者： Ngo, Kalle Mohammadat, Tage Oberg, Johnny Department of Electronics School of Information and Communication Technology KTH Royal Institute of Technology Stockholm Sweden

ISBN: (纸本)9781538628447

The Single Event Upset Detector (SEUD) is 3U CubeSat payload experiment that aims to achieve radiation tolerant computing through detection and correction of SEU bit flips on COTS SRAM FPGAs. Our proposed self-healing architecture applies selective TMR, internal configuration memory scrubbing, and partial reconfiguration and intends to demonstrate a cost-effective alternative to Space-grade radiation hardened SRAM FPGAs. This paper presents an overview of the ongoing development of the SEUD architecture and when complete, the SEUD will be tested on board the KTH MIST student CubeSat that is targeting to be launched in late 2020. © 2017 IEEE.

关键词： field programmable gate arrays (FPGA)

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Parallel hardware-software architecture for computation of Discrete Wavelet Transform using the Recursive Merge Filtering algorithm

Parallel hardware-software architecture for computation of D...

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IEEE international Parallel and Distributed Processing symposium (IPDPS 2000)

作者： Jamkhandi, P Mukherjee, A Mukherjee, K Franceschini, R Univ Cent Florida Sch Elect Engn & Comp Sci Orlando FL 32816 USA

ISBN: (纸本)354067442X

We present an FPGA-based parallel hardware-software architecture for the computation of the Discrete Wavelet Transform (DWT), using the Recursive Merge Filtering (RMF) algorithm. The DWT is built in a bottom-up fashion in logN steps, successively building complete DWTs by "merging" two smaller DWTs and applying the wavelet filter to only the "smooth" or DC coefficient from the smaller DWTs. The main bottleneck of this algorithm is the data routing process, which can be reduced by separating the computations into two types to introduce parallelism. This is achieved by using a virtual mapping structure to map the input. The data routing bottleneck has been transformed into simple arithmetic computations on the mapping structure. Due to the use of the FPGA-RAM for the mapping structure, the total number of data accesses to the main memory are reduced. This architecture shows how data routing in this problem can be transformed into a series of index computations.

关键词： field programmable gate arrays (FPGA)

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Emerging application domains: research challenges and opportunities for FPGAs 09

Emerging application domains: research challenges and opport...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Jason H. Anderson University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

Communications infrastructure, data processing and industrial electronics are the cornerstone application areas for programmable logic today. But what are the application domains of tomorrow? What nascent application areas could explode the growth of programmable logic usage and expand the programmable market? In this workshop, we will hear speakers from industry and academia talk about the emerging application areas for FPGAs and the challenges and opportunities in these areas. We will consider how programmable hardware and the associated tools should be enhanced to become better-suited to tomorrow's applications. The overarching aim of the workshop is to seed ideas in the research community by giving an applications perspective of the fertile topics for future research on FPGA architecture, CAD and applications.

关键词： high-performance computing field-programmable gate array applications performance power fpga reconfigurable computing

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HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond 24

HLSFactory: A Framework Empowering High-Level Synthesis Data...

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6th international symposium on Machine Learning for CAD (MLCAD)

作者： Abi-Karam, Stefan Sarkar, Rishov Seigler, Allison Lowe, Sean Wei, Zhigang Chen, Hanqiu Rao, Nanditha John, Lizy Arora, Aman Hao, Cong Georgia Inst Technol Atlanta GA 30332 USA Georgia Tech Res Inst Atlanta GA 30332 USA Univ Texas Austin Austin TX USA Arizona State Univ Tempe AZ USA Int Inst Informat Technol Bangalore Bangalore Karnataka India

ISBN: (数字)9798350363562

ISBN: (纸本)9798400706998

Machine learning (ML) techniques have been applied to high-level synthesis (HLS) flows for quality-of-result (QoR) prediction and design space exploration (DSE). Nevertheless, the scarcity of accessible highquality HLS datasets and the complexity of building such datasets present great challenges to FPGA and ML researchers. Existing datasets either cover only a subset of previously published benchmarks, provide no way to enumerate optimization design spaces, are limited to a specific vendor, or have no reproducible and extensible software for dataset construction. Many works also lack user-friendly ways to add more designs to existing datasets, limiting wider adoption and sustainability of such datasets. In response to these challenges, we introduce HLSFactory, a comprehensive framework designed to facilitate the curation and generation of high-quality HLS design datasets. HLSFactory has three main stages: 1) a design space expansion stage to elaborate single HLS designs into large design spaces using various optimization directives across multiple vendor tools, 2) a design synthesis stage to execute HLS and FPGA tool flows concurrently across designs, and 3) a data aggregation stage for extracting standardized data into packaged datasets for ML usage. This tripartite architecture not only ensures broad coverage of data points via design space expansion but also supports interoperability with tools from multiple vendors. Users can contribute to each stage easily by submitting their own HLS designs or synthesis results via provided user APIs. The framework is also flexible, allowing extensions at every step via user APIs with custom frontends, synthesis tools, and scripts. To demonstrate the framework functionality, we include an initial set of built-in base designs from PolyBench, MachSuite, Rosetta, CHStone, Kastner et al.'s Parallel Programming for FPGAs, and curated kernels from existing open-source HLS designs. We report the statistical analyses and design space

关键词： Solid modeling Statistical analysis Buildings Machine learning Benchmark testing Software Space exploration Sustainable development field programmable gate arrays Optimization

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Plasma: An FPGA for Million gate Systems

Plasma: An FPGA for Million Gate Systems

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： R. Amerson R. Carter W. Culbertson P. Kuekes G. Snider L. Albertson Hewlett Packard Laboratories Palo Alto CA USA Hewlett-Packard California Design Center Palo Alto CA USA

Prototypes are invaluable for studying special purpose parallel architectures and custom computing. This paper describes a new FPGA, called Plasma- the heart of a configurable custom computing engine (Teramac) that can execute synchronous logic designs up to one million gates at rates up to one megahertz. Plasma FPGA's using 0.8 micron CMOS are packaged in large multichip modules (MCMs). A large custom circuit may be mapped onto the hardware in approximately two hours, without user intervention. Plasma introduces some innovative architecture concepts including hardware support for large multiported register files.

关键词： field programmable gate arrays Plasma applications Hardware Prototypes Parallel architectures Concurrent computing Heart Engines Logic design Packaging

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High-Energy Physics on DECPeRLe-1 programmable Active Memory

High-Energy Physics on DECPeRLe-1 Programmable Active Memory

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： L. Moll J. Vuillemin P. Boucard Supérieure des Télécommunications Paris France Pôle Universitaire Léonard-de-Vinci La Defense France Matra-Harris Semiconductors Saint-Quentin-en-Yvelines France

The future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST (RD-11) group and DECPRL PAM team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.

关键词： Physics field programmable gate arrays

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Configurable FPGA-Based Outlier Detection for Time Series Data 63

Configurable FPGA-Based Outlier Detection for Time Series Da...

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63rd IEEE international Midwest symposium on Circuits and Systems (MWSCAS)

作者： MacEachern, Leonard Vazhbakht, Ghazaleh Carleton Univ Dept Elect Ottawa ON K1S 5B6 Canada

ISBN: (数字)9781728180588

ISBN: (纸本)9781728180588

An outlier detection technique based on joint estimation of model parameters and outlier effects in time series is implemented in FPGA-based configurable real-time outlier detection hardware. The hardware models time series data with an autoregressive-moving-average (ARMA) process and identifies the outliers based on test statistics using unbiased parameters. A configurable hardware implementation was written in Verilog, simulated to verify its correctness, and synthesized on an Altera FPGA device from the Stratix V family. The design is configurable by adjusting the number of iterations for the optimization process, the number of samples in the time series data, and the critical value. A reported configuration of this design has a total power dissipation of 1.14W, while processing 35 million data points per second, giving an energy usage of 32 nJ per processed data point. The implemented hardware is capable of detecting multiple additive outliers in time series data with a detection accuracy of 99% and has a type I error rate of 1.05%. Compared to a general purpose CPU running a software implementation of the outlier detection algorithm, the FPGA implementation reduces the power consumption by 89% at similar rates of data throughput.

关键词： Time series analysis Hardware Anomaly detection field programmable gate arrays Data models Optimization Additives

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