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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors (abstract only) 13

Hardware acceleration of TEA and XTEA algorithms on FPGA, GP...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Vivek Venugopal Devu Manikantan Shila United Technologies Research Center E Hartford CT USA

ISBN: (纸本)9781450318877

field programmable gate arrays (FPGA) are extensively used for rapid prototyping in embedded system applications. While hardware acceleration can be done via specialized processors like a Graphical Processing Unit (GPU), they can also be accomplished with FPGAs for more specialized scenarios. GPUs essentially consist of massively parallel cores and have high memory bandwidth; FPGAs, on the other hand, provide flexibility in terms of customizable I/O and computational resources. In this paper, we explore the usage of GPUs and FPGAs as cryptographic co-processors in streaming dataflow systems with huge rate of data inhalation. Two classic lightweight encryption algorithms, Tiny Encryption Algorithm (TEA) and Extended Tiny Encryption Algorithm (XTEA), are targeted for implementation on GPUs and FPGAs. The GPU implementations of TEA and XTEA in this study depict a maximum speedup of 13x over CPU based implementation. The pipelined FPGA implementation is able to realize a throughput of 6-9x more than the GPU for small plaintext sizes.

关键词： cryptography graphics processing units tiny encryption algorithm field programmable gate arrays parallel processing

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A Configurable Cloud-Scale DNN Processor for Real-Time AI 18

A Configurable Cloud-Scale DNN Processor for Real-Time AI

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45th acm/IEEE Annual international symposium on Computer Architecture (ISCA)

作者： Fowers, Jeremy Ovtcharov, Kalin Papamichael, Michael Massengill, Todd Liu, Ming Lo, Daniel Alkalay, Shlomi Haselman, Michael Adams, Logan Ghandi, Mahdi Heil, Stephen Patel, Prerak Sapek, Adam Weisz, Gabriel Woods, Lisa Lanka, Sitaram Reinhardt, Steven K. Caulfield, Adrian M. Chung, Eric S. Burger, Doug Microsoft Redmond WA 98052 USA

ISBN: (纸本)9781538659847

Interactive AI-powered services require low-latency evaluation of deep neural network (DNN) models-aka "real-time Al". The growing demand for computationally expensive, state-of-the-art DNNs, coupled with diminishing performance gains of general-purpose architectures, has fueled an explosion of specialized Neural Processing Units (NPUs). NPUs for interactive services should satisfy two requirements: (1) execution of DNN models with low latency, high throughput, and high efficiency, and (2) flexibility to accommodate evolving state-of-the-art models (e.g., RNNs, CNNs, MLPs) without costly silicon updates. This paper describes the NPU architecture for Project Brain-wave, a production-scale system for real-time AI. The Brainwave NPU achieves more than an order of magnitude improvement in latency and throughput over state-of-the-art GPUs on large RNNs at a batch size of 1. The NPU attains this performance using a single-threaded SIMD ISA paired with a distributed microarchitecture capable of dispatching over 7M operations from a single instruction. The spatially distributed microarchitecture, scaled up to 96,000 multiply-accumulate units, is supported by hierarchical instruction decoders and schedulers coupled with thousands of independently addressable high-bandwidth on-chip memories, and can transparently exploit many levels of fine-grain SIMD parallelism. When targeting an FPGA, microarchitectural parameters such as native datapaths and numerical precision can be "synthesis specialized" to models at compile time, enabling high FPGA performance competitive with hardened NPUs. When running on an Intel Stratix 10 280 FPGA, the Brainwave NPU achieves performance ranging from ten to over thirty-five teraflops, with no batching, on large, memory-intensive RNNs.

关键词： neural network hardware accelerator architectures field programmable gate arrays

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Panel: Attack of the killer gate arrays 03

Panel: Attack of the killer gate arrays

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proceedings of the 2003 acm/sigda eleventh international symposium on field programmable gate arrays

作者： Michael Butts Jonathan Rose Steve Trimberger Herman Schmit Cadence Altera Xilinx CMU

ISBN: (纸本)9781581136517

The ever-growing capacity and speed of FPGAs have brought them into the heart of the silicon mainstream. Major ASIC vendors have responded by reviving masterslice gate arrays, standard prefab die with design-specific metal layers. They claim lower NREs, quicker delivery and easier design than cell-based ASICs, and lower unit cost, better speed, capacity and power than *** these gate arrays spell doom for FPGA vendors' dreams of displacing the ASIC as a mainstream silicon platform?Will the FPGA's high volume, superior flexibility and time-to-market prevail?Will FPGA's co-exist in different classes of application?A panel of experts from FPGA and ASIC vendors and academia will duke it out. Each panelist will give a short presentation putting forward their point of view followed by an interactive debate among the panelists and attendees.

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Fast and memory efficient approximated convex hull computation with FPGA 8

Fast and memory efficient approximated convex hull computati...

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8th international symposium on Computing and Networking, CANDAR 2020

作者： Mori, Tatsuma Manabe, Taito Shibata, Yuichiro Nagasaki University Japan

ISBN: (纸本)9781728182216

The convex hull is the minimum convex set surrounding a set of points. The process of finding the convex hull has many application fields, including embedded applications on power-limbered and real-time systems. In general, such systems are preferably implemented with FPGAs. In order to compute the convex hull of an unsorted point set, it is necessary to store all the points during the computation, and thus the capacity of a on-chip memory is likely to be a major constraint for efficient FPGA implementation. On the other hand, approximated convex hulls are often sufficient for practical applications. Therefore, in this paper, we proposed an algorithm that computes an approximated convex hull without storing all unsorted points, and presented its FPGA implementation to evaluate the effectiveness. As a result, we achieved 11 to 30 times faster performance compared to the widely-used convex hull computation library Qhull. In addition, quality comparisons revealed that the maximum approximation error normalized to the diameters of point sets was 0.038%, which was reasonably small for practical use cases. © 2020 IEEE

关键词： field programmable gate arrays (FPGA)

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FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud 18

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simul...

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45th acm/IEEE Annual international symposium on Computer Architecture (ISCA)

作者： Karandikar, Sagar Mao, Howard Kim, Donggyu Biancolin, David Amid, Alon Lee, Dayeol Pemberton, Nathan Amaro, Emmanuel Schmidt, Colin Chopra, Aditya Huang, Qijing Kovacs, Kyle Nikolic, Borivoje Katz, Randy Bachrach, Jonathan Asanovic, Krste Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781538659847

We present FireSim, an open-source simulation platform that enables cycle-exact microarchitectural simulation of large scale-out clusters by combining FPGA-accelerated simulation of silicon-proven RTL designs with a scalable, distributed network simulation. Unlike prior FPGA-accelerated simulation tools, FireSim runs on Amazon EC2 Fl, a public cloud FPGA platform, which greatly improves usability, provides elasticity, and lowers the cost of large-scale FPGA-based experiments. We describe the design and implementation of FireSim and show how it can provide sufficient performance to run modern applications at scale, to enable true hardware-software co-design. As an example, we demonstrate automatically generating and deploying a target cluster of 1,024 3.2 GHz quad-core server nodes, each with 16 GB of DRAM, interconnected by a 200 Gbit/s network with 2 microsecond latency, which simulates at a 3.4 MHz processor clock rate (less than 1,000x slowdown over real-time). In aggregate, this FireSim instantiation simulates 4,096 cores and 16 TB of memory, runs-14 billion instructions per second, and harnesses 12.8 million dollars worth of FPGAs at a total cost of only 1100 per simulation hour to the user. We present several examples to show how FireSim can be used to explore various research directions in warehouse-scale machine design, including modeling networks with high-bandwidth and low-latency, integrating arbitrary RTL designs for a variety of commodity and specialized datacenter nodes, and modeling a variety of datacenter organizations, as well as reusing the scale-out FireSim infrastructure to enable fast, massively parallel cycle-exact single-node microarchitectural experimentation.

关键词： Data centers Computer simulation field programmable gate arrays Computer networks Distributed computing Performance analysis Scalability Computer architecture

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PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs

PathFinder: A Negotiation-Based Performance-Driven Router fo...

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： L. McMurchie C. Ebeling Department of Computer Science and Engineering University of Washington Seattle WA USA

Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router that balances the goals of performance and routability. PathFinder uses an iterative algorithm that converges to a solution in which all signals are routed while achieving close to the optimal performance allowed by the placement. Routability is achieved by forcing signals to negotiate for a resource and thereby determine which signal needs the resource most. Delay is minimized by allowing the more critical signals a greater say in this negotiation. Because PathFinder requires only a directed graph to describe the architecture of routing resources, it adapts readily to a wide variety of FPGA architectures such as Triptych, Xilinx 3000 and mesh-connected arrays of FPGAs. The results of routing ISCAS benchmarks on the Triptych FPGA architecture show an average increase of only 4.5% in critical path delay over the optimum delay for a placement. Routes of ISCAS benchmarks on the Xilinx 3000 architecture show a greater completion rate than commercial tools, as well as 11% faster implementations.

关键词： field programmable gate arrays Routing Delay Application specific integrated circuits Computer science Wires Wiring Iterative algorithms Adaptive arrays Resource management

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Trusted Electronic Systems with Untrusted COTS 22

Trusted Electronic Systems with Untrusted COTS

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22nd international symposium on Quality Electronic Design (ISQED)

作者： Yang, Shuo Chakraborty, Prabuddha Slpsk, Patanjali Bhunia, Swarup Univ Florida Gainesville FL 32611 USA

ISBN: (纸本)9781728176413

The challenges of custom integrated circuits (IC) design have made it prevalent to integrate commercial-off-the-shelf (COTS) components (micro-controllers, FPGAs, etc.) in today's designs. While this approach eases the design challenges and improves productivity, it also gives rise to diverse security concerns. One such concern is the possibility of malicious hardware modifications, also called hardware Trojan attacks, by untrusted parties involved in the manufacturing or distribution of COTS devices. While Hardware Trojan detection is an active research topic in the field of microelectronics security, most methods assume the availability of a golden design/chip, which is impractical in the case of a COTS device. In this paper, we discuss challenges with detecting Trojan in COTS components, and introduce a Trojan detection method that applies unsupervised learning. We utilize side-channel power signatures to cluster and isolate chips with Trojans. The proposed method is suitable for trust verification of COTS components by an original equipment manufacturer (OEM) before system integration. In our method, the design house creates a set of security validation test vectors available to the tester (e.g., OEM). The OEM can also generate the test vectors using the block-level diagrams provided by the design house. Power signatures are generated for all the chips under test using these test vectors. We use the generated power signatures to apply feature extraction followed by clustering to group the chips into bins. Through this process, we divide the chips into distinct bins and distinguish the Trojan-inserted chips from the Trojan-free ones. The bin with golden chips can be identified by extensive testing and reverse engineering of one chip sampled from each bin. We utilize two clustering techniques K-Means, and Expectation-Maximization (EM) to perform a comparative analysis. Additionally, we perform extensive experiments to assert our method's effectiveness and obtain o

关键词： field programmable gate arrays (FPGA)

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CJS: Custom Jacobi Solver 2018

CJS: Custom Jacobi Solver

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9th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Cross, Andreea-Ingrid Guo, Liucheng Luk, Wayne Salmon, Mark Imperial Coll London London England Univ Cambridge Cambridge England

ISBN: (纸本)9781450365420

The classic Jacobi method, widely used for solving linear systems, is slow, especially when dealing with large matrices. This paper proposes a Custom Jacobi Solver (CJS) for large-scale linear systems. It is based on a column-wise Jacobi step operation which allows for increased dependence distance, enabling deep pipelining. Our solver allows customisation at run time between the classic Jacobi method and its more convergence efficient-counterpart, the weighted Jacobi method. It can be dynamically scaled to multiple FPGAs by appropriately partitioning the matrix data among the FPGAs. After evaluating our solver on a number of different datasets, CJS proves to be up to 71 times faster when comparing an 8-FPGA solution with a 12-core CPU C++ implementation.

关键词： field programmable gate arrays (FPGA)

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FPGA-based HPC application design for non-experts (abstract only) 13

FPGA-based HPC application design for non-experts (abstract ...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： David Uliana Krzysztof Kepa Peter Athanas Virginia Tech Blacksburg VA USA

ISBN: (纸本)9781450318877

This paper presents bFlow, an FPGA development framework for the rapid prototyping and implementation of hardware accelerators for hybrid computing platforms. This framework makes use of an abstracted, graphical front-end usable by those without computer engineering backgrounds, as well as an accelerated back-end that speeds up compilation times, increasing turns-per-day. bFlow's performance, usability, and application to the acceleration of big-data life-science problems verified by participants of the NSF-funded Summer Institute organised by the Virginia Bioinformatics Institute (VBI). In less than two weeks, a group of four non-computer science/computer engineering participants made modifications to a reference Smith-Waterman implementation, adding functionality and scaling throughput by a factor of four to 600 million base pairs per second.

关键词： field-programmable gate arrays bioinformatics co-processor heterogeneous computing design productivity convey HC-1 big-data

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FPGA and ASIC Implementation and Comparison of Multipliers 3

FPGA and ASIC Implementation and Comparison of Multipliers

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3rd international symposium on Devices, Circuits and Systems, ISDCS 2020

作者： Neyaz, Salwa Yasmeen Saxena, Itisha Alam, Naushad Rahman, Syed Atiqur Department of Electronics Engineering Aligarh India

ISBN: (纸本)9781728165646

The multipliers find extensive use in today's digital world and are even fundamental components in many signal processing applications. This paper presents the implementation and comparison of three types of 4-bit and 8-bit multipliers i.e. Array, Wallace and Baugh Wooley. The implementation is done on both the FPGA and ASIC to compare the designs. The FPGA implementation is done on NEXYS 4 DDR which is equipped with Xilinx Artix-7 FPGA. The ASIC implementation is done using Cadence and Standard Cell Library 90 nm gpdk (generic process design kit). The results indicate that the Baugh Wooley incurs the minimum delay in the FPGA implementation while as the Wallace tree incurs minimum Power Delay Product in the ASIC implementation. The Baugh Wooley is the least area consuming architecture for both the FPGA and the ASIC implementation. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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