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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Design Guidelines for Embeded NoCs on FPGAs 17

Design Guidelines for Embeded NoCs on FPGAs

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17th international symposium on Quality Electronic Design (ISQED)

作者： Gamal, Noha Fahmy, Hossam Ismail, Yehea Mostafa, Hassan Mentor Graph Corp Wilsonville OR 97070 USA Cairo Univ Elect & Commun Engn Dept Giza 12613 Egypt Zewail City Sci & Technol CND Giza Egypt AUC New Cairo 11835 Egypt

ISBN: (纸本)9781509012138

Including Networks-on-Chip (NoCs) within FPGAs has become necessary to overcome the problems of point-to-point interconnect scheme. This will enable interfacing with high speed IOs and partial dynamic reconfiguration (PDR), reduce the compile time and improve the system performance. We compared FPGA-specific NoC components on soft and hard implementations and analyzed the efficiency gap between the two technologies to get design constraints in this space. Input module that includes memory buffers, implemented using block RAMs (BRAMs), is the module with the smallest gaps: 1.8x area, 2.9x delay and 53x power. Switch has the largest gap: 90x area, 7x delay and 53x power. If the router is totally hard implemented, this will save 9x area, 3.7x delay and 12x power at the expense of no flexibility (reconfigurability). By comparing our results with same flow on ASIC-specific router, we show that using FPGA-specific NoCs design improves the utility by a factor of 3x in area with a slight increase in the delay.

关键词： field programmable gate arrays (FPGA)

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Acceleration of Synthetic Aperture Radar (SAR) Algorithms using field programmable gate arrays (FPGAs) (Abstract Only) 15

Acceleration of Synthetic Aperture Radar (SAR) Algorithms us...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Youngsoo Kim William Harding Clay S. Gloster Winser Alexander North Carolina A&T State University Greensboro NC USA North Carolina State University Raleigh NC USA

ISBN: (纸本)9781450333153

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, field programmable gate arrays (FPGAs) can be used to house hardware-based custom implementations of these kernels to speed up these applications. In this paper, we demonstrate a methodology for algorithm acceleration. We used SAR as a case study to illustrate the tremendous potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show an average speed-up of 188 when using the FPGA-based hardware accelerator as opposed to using a software implementation running on a typical general purpose processor.

关键词： floating point fpga logarithmic synthetic aperture radar homomorphic

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HGA: A Hardware-Based Genetic Algorithm

HGA: A Hardware-Based Genetic Algorithm

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： S.D. Scott A. Samal S. Seth Department of Computer Science Washington University Saint Louis MO USA Department of Computer Science and Engineering University of Nebraska Lincoln Lincolnshire NE USA

A genetic algorithm (GA) is a robust problem-solving method based on natural selection. Hardware's speed advantage and its ability to parallelize offer great rewards to genetic algorithms. Speedups of 1-3 orders of magnitude have been observed when frequently used software routines were implemented in hardware by way of reprogrammable field-programmable gate arrays (FPGAs). Reprogrammability is essential in a general-purpose GA engine because certain GA modules require changeability (e.g. the function to be optimized by the GA). Thus a hardware-based GA is both feasible and desirable. A fully functional hardware-based genetic algorithm (the HGA) is presented here as a proof-of-concept system. It was designed using VHDL to allow for easy scalability. It is designed to act as a coprocessor with the CPU of a PC. The user programs the FPGAs which implement the function to be optimized. Other GA parameters may also be specified by the user. Simulation results and performance analyses of the HGA are presented. A prototype HGA is described and compared to a similar GA implemented in software. In the simple tests, the prototype took about 6% as many clock cycles to run as the software-based GA. Further suggested improvements could realistically make the HGA 2-3 orders of magnitude faster than the software-based GA.

关键词： Genetic algorithms field programmable gate arrays Hardware Software prototyping Robustness Problem-solving Engines Scalability Coprocessors Design optimization

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An Automated Design Framework for Floating Point Scientific Algorithms using field programmable gate arrays (FPGAs) (Abstract Only) 15

An Automated Design Framework for Floating Point Scientific ...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Michaela E. Amoo Youngsoo Kim Vance Alford Shrikant Jadhav Naser I. El-Bathy Clay S. Gloster Jr. Howard University Washington DC USA North Carolina A&T State University Greensboro NC USA

ISBN: (纸本)9781450333153

This paper presents a reconfigurable computing environment while addressing the problem of porting High Performance Computing (HPC) applications directly to field programmable gate arrays (FPGAs)-based architectures. The objectives of this research are developing a comprehensive floating point library of essential functions for scientific applications; demonstrate order of magnitude speedup of reconfigurable computing applications, demonstrating the effectiveness of automated design framework for both development and test of scientific algorithms. The developed framework can be reused in various scientific applications which shares kernel functions. The study of this research has identified an exponential function as a kernel for cellular ophthalmoscopy camera processing, traffic monitoring and light wave simulation. The paper demonstrates 30x speedup of these kernels in three algorithms using its novel architecture and its automated toolset. Exponential kernel generation case study and its flexible hardware implementation on an FPGA has been validated onto a Xilinx LX-100 device and the Nallatech H101-PCIXM FPGA board.

关键词： floating point exponential hpc fpga

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Fast and memory efficient approximated convex hull computation with FPGA 8

Fast and memory efficient approximated convex hull computati...

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8th international symposium on Computing and Networking, CANDAR 2020

作者： Mori, Tatsuma Manabe, Taito Shibata, Yuichiro Nagasaki University Japan

ISBN: (纸本)9781728182216

The convex hull is the minimum convex set surrounding a set of points. The process of finding the convex hull has many application fields, including embedded applications on power-limbered and real-time systems. In general, such systems are preferably implemented with FPGAs. In order to compute the convex hull of an unsorted point set, it is necessary to store all the points during the computation, and thus the capacity of a on-chip memory is likely to be a major constraint for efficient FPGA implementation. On the other hand, approximated convex hulls are often sufficient for practical applications. Therefore, in this paper, we proposed an algorithm that computes an approximated convex hull without storing all unsorted points, and presented its FPGA implementation to evaluate the effectiveness. As a result, we achieved 11 to 30 times faster performance compared to the widely-used convex hull computation library Qhull. In addition, quality comparisons revealed that the maximum approximation error normalized to the diameters of point sets was 0.038%, which was reasonably small for practical use cases. © 2020 IEEE

关键词： field programmable gate arrays (FPGA)

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QuickRec: Prototyping an intel architecture extension for record and replay of multithreaded programs 13

QuickRec: Prototyping an intel architecture extension for re...

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40th Annual international symposium on Computer Architecture, ISCA 2013

作者： Pokam, Gilles Danne, Klaus Pereira, Cristiano Kassa, Rolf Kranich, Tim Hu, Shiliang Gottschlich, Justin Honarmand, Nima Dautenhahn, Nathan King, Samuel T. Torrellas, Josep Intel Corporation United States University of Illinois Urbana-Champaign United States

ISBN: (纸本)9781450320795

There has been significant interest in hardware-assisted deterministic Record and Replay (RnR) systems for multithreaded programs on multiprocessors. However, no proposal has implemented this technique in a hardware prototype with full operating system support. Such an implementation is needed to assess RnR practicality. This paper presents QuickRec, the first multicore Intel Architecture (IA) prototype of RnR for multithreaded programs. QuickRec is based on QuickIA, an Intel emulation platform for rapid prototyping of new IA extensions. QuickRec is composed of a Xeon server platform with FPGA-emulated second-generation Pentium cores, and Capo 3, a full software stack for managing the recording hardware from within a modified Linux kernel. This paper's focus is understanding and evaluating the implementation issues of RnR on a real platform. Our effort leads to some lessons learned, as well as to some pointers for future research. We demonstrate that RnR can be implemented efficiently on a real multicore IA system. In particular, we show that the rate of memory log generation is insignificant, and that the recording hardware has negligible performance overhead. However, the software stack incurs an average recording overhead of nearly 13%, which must be reduced to enable always-on use of RnR. Copyright 2013 acm.

关键词： field programmable gate arrays (FPGA)

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The EPAC architecture: an expert cell approach to field programmable analog devices 96

The EPAC architecture: an expert cell approach to field prog...

引用

proceedings of the 1996 acm fourth international symposium on field-programmable gate arrays

作者： Hans W. Klein IMP Inc. San Jose CA

No abstract available.

ISBN: (纸本)9780897917735

No abstract available.

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Trusted Electronic Systems with Untrusted COTS 22

Trusted Electronic Systems with Untrusted COTS

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22nd international symposium on Quality Electronic Design (ISQED)

作者： Yang, Shuo Chakraborty, Prabuddha Slpsk, Patanjali Bhunia, Swarup Univ Florida Gainesville FL 32611 USA

ISBN: (纸本)9781728176413

The challenges of custom integrated circuits (IC) design have made it prevalent to integrate commercial-off-the-shelf (COTS) components (micro-controllers, FPGAs, etc.) in today's designs. While this approach eases the design challenges and improves productivity, it also gives rise to diverse security concerns. One such concern is the possibility of malicious hardware modifications, also called hardware Trojan attacks, by untrusted parties involved in the manufacturing or distribution of COTS devices. While Hardware Trojan detection is an active research topic in the field of microelectronics security, most methods assume the availability of a golden design/chip, which is impractical in the case of a COTS device. In this paper, we discuss challenges with detecting Trojan in COTS components, and introduce a Trojan detection method that applies unsupervised learning. We utilize side-channel power signatures to cluster and isolate chips with Trojans. The proposed method is suitable for trust verification of COTS components by an original equipment manufacturer (OEM) before system integration. In our method, the design house creates a set of security validation test vectors available to the tester (e.g., OEM). The OEM can also generate the test vectors using the block-level diagrams provided by the design house. Power signatures are generated for all the chips under test using these test vectors. We use the generated power signatures to apply feature extraction followed by clustering to group the chips into bins. Through this process, we divide the chips into distinct bins and distinguish the Trojan-inserted chips from the Trojan-free ones. The bin with golden chips can be identified by extensive testing and reverse engineering of one chip sampled from each bin. We utilize two clustering techniques K-Means, and Expectation-Maximization (EM) to perform a comparative analysis. Additionally, we perform extensive experiments to assert our method's effectiveness and obtain o

关键词： field programmable gate arrays (FPGA)

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The Wave Pipeline Effect on LUT-Based FPGA Architectures

The Wave Pipeline Effect on LUT-Based FPGA Architectures

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： E.I. Boemo S. Lopez-Buedo J.M. Meneses E.T.S.I. Telecomunicación Ciudad Universitaria Madrid Spain

The wave pipeline effect is based on the equalization of all path delays in order to allow several "waves" of data to travel along the circuit with a separation several times smaller than the maximum combinational delay of the circuit. The construction of wave pipelines requires gates and buffers with data-independent delay, and a well-characterized interconnection network delay model, in order to allow the equalization process to be managed by the designer. These features are inherently present in several RAM-based FPGAs architectures. Look-up tables (LUTs) permit the delay of digital blocks with different types of gates or different logic depth to be equalized; moreover, the delay of a FPGA interconnection network is completely parameterized and is a priori known. This paper describes a LUT-based wave pipeline array multiplier manually implemented using a Xilinx chip. The results show that, even for a single-phase non-skewed clocking strategy, a throughput as high as 85 MHz (measured) can be achieved, with 8 waves running in a 13-LUT logic depth combinational array with registered I/O, producing an initial latency of 9 clock cycles. For the FPGA architecture and the topology selected, such a large throughput/latency ratio would be impossible using classical pipelininig.

关键词： Pipelines field programmable gate arrays Propagation delay Delay effects Circuits Multiprocessor interconnection networks Clocks Throughput Logic arrays Table lookup

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Universal Logic Modules for Series-Parallel Functions

Universal Logic Modules for Series-Parallel Functions

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proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： S. Thakur D.F. Wong Department of Computer Science University of Technology Austin USA

The need for a two-way interaction between logic synthesis and FPGA logic module design has been stressed recently. Having a logic module that can implement many functions is a good idea only if one can also give a synthesis strategy that makes efficient use of this funtionality. Traditionally technology mapping algorithms have been developed after the logic architecture has been designed. We follow a dual approach, by focusing on a specific technology mapping algorithm, namely the structural tree-based mapping algorithm, and designing a logic module that can be mapped efficiently by this algorithm. It is known that the tree-based mapping algorithm makes optimal use of a library of funtions, each of which can be represented by a tree of AND, OR and NOT gates (series-parallel or SP functions). We show how to design a SP function with a minimum number of inputs, that can implement all possible SP functions with a specified number of inputs. For instance, we demonstrate a 7-input SP function that can implement all 4-input SP functions. Mapping results show that, on an average, the number blocks of this function needed to map benchmark circuits is 12% less than that for Actel's ACT1 logic modules. Our logic modules show a 4% improvement over ACT1, if the block count is scaled to take into account the number of transistors needed to implement different logic modules.

关键词： Logic arrays field programmable gate arrays

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