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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"
834 条 记 录,以下是721-730 订阅
排序:
Design Guidelines for Embeded NoCs on FPGAs  17
Design Guidelines for Embeded NoCs on FPGAs
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17th international symposium on Quality Electronic Design (ISQED)
作者: Gamal, Noha Fahmy, Hossam Ismail, Yehea Mostafa, Hassan Mentor Graph Corp Wilsonville OR 97070 USA Cairo Univ Elect & Commun Engn Dept Giza 12613 Egypt Zewail City Sci & Technol CND Giza Egypt AUC New Cairo 11835 Egypt
Including Networks-on-Chip (NoCs) within FPGAs has become necessary to overcome the problems of point-to-point interconnect scheme. This will enable interfacing with high speed IOs and partial dynamic reconfiguration ... 详细信息
来源: 评论
Acceleration of Synthetic Aperture Radar (SAR) Algorithms using field programmable gate arrays (FPGAs) (Abstract Only)  15
Acceleration of Synthetic Aperture Radar (SAR) Algorithms us...
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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays
作者: Youngsoo Kim William Harding Clay S. Gloster Winser Alexander North Carolina A&T State University Greensboro NC USA North Carolina State University Raleigh NC USA
Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to ... 详细信息
来源: 评论
HGA: A Hardware-Based Genetic Algorithm
HGA: A Hardware-Based Genetic Algorithm
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proceedings of the acm international symposium on field-programmable gate arrays, FPGA
作者: S.D. Scott A. Samal S. Seth Department of Computer Science Washington University Saint Louis MO USA Department of Computer Science and Engineering University of Nebraska Lincoln Lincolnshire NE USA
A genetic algorithm (GA) is a robust problem-solving method based on natural selection. Hardware's speed advantage and its ability to parallelize offer great rewards to genetic algorithms. Speedups of 1-3 orders o... 详细信息
来源: 评论
An Automated Design Framework for Floating Point Scientific Algorithms using field programmable gate arrays (FPGAs) (Abstract Only)  15
An Automated Design Framework for Floating Point Scientific ...
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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays
作者: Michaela E. Amoo Youngsoo Kim Vance Alford Shrikant Jadhav Naser I. El-Bathy Clay S. Gloster Jr. Howard University Washington DC USA North Carolina A&T State University Greensboro NC USA
This paper presents a reconfigurable computing environment while addressing the problem of porting High Performance Computing (HPC) applications directly to field programmable gate arrays (FPGAs)-based architectures. ... 详细信息
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Fast and memory efficient approximated convex hull computation with FPGA  8
Fast and memory efficient approximated convex hull computati...
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8th international symposium on Computing and Networking, CANDAR 2020
作者: Mori, Tatsuma Manabe, Taito Shibata, Yuichiro Nagasaki University Japan
The convex hull is the minimum convex set surrounding a set of points. The process of finding the convex hull has many application fields, including embedded applications on power-limbered and real-time systems. In ge... 详细信息
来源: 评论
QuickRec: Prototyping an intel architecture extension for record and replay of multithreaded programs  13
QuickRec: Prototyping an intel architecture extension for re...
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40th Annual international symposium on Computer Architecture, ISCA 2013
作者: Pokam, Gilles Danne, Klaus Pereira, Cristiano Kassa, Rolf Kranich, Tim Hu, Shiliang Gottschlich, Justin Honarmand, Nima Dautenhahn, Nathan King, Samuel T. Torrellas, Josep Intel Corporation United States University of Illinois Urbana-Champaign United States
There has been significant interest in hardware-assisted deterministic Record and Replay (RnR) systems for multithreaded programs on multiprocessors. However, no proposal has implemented this technique in a hardware p... 详细信息
来源: 评论
The EPAC architecture: an expert cell approach to field programmable analog devices  96
The EPAC architecture: an expert cell approach to field prog...
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proceedings of the 1996 acm fourth international symposium on field-programmable gate arrays
作者: Hans W. Klein IMP Inc. San Jose CA
No abstract available.
来源: 评论
Trusted Electronic Systems with Untrusted COTS  22
Trusted Electronic Systems with Untrusted COTS
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22nd international symposium on Quality Electronic Design (ISQED)
作者: Yang, Shuo Chakraborty, Prabuddha Slpsk, Patanjali Bhunia, Swarup Univ Florida Gainesville FL 32611 USA
The challenges of custom integrated circuits (IC) design have made it prevalent to integrate commercial-off-the-shelf (COTS) components (micro-controllers, FPGAs, etc.) in today's designs. While this approach ease... 详细信息
来源: 评论
The Wave Pipeline Effect on LUT-Based FPGA Architectures
The Wave Pipeline Effect on LUT-Based FPGA Architectures
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proceedings of the acm international symposium on field-programmable gate arrays, FPGA
作者: E.I. Boemo S. Lopez-Buedo J.M. Meneses E.T.S.I. Telecomunicación Ciudad Universitaria Madrid Spain
The wave pipeline effect is based on the equalization of all path delays in order to allow several "waves" of data to travel along the circuit with a separation several times smaller than the maximum combina... 详细信息
来源: 评论
Universal Logic Modules for Series-Parallel Functions
Universal Logic Modules for Series-Parallel Functions
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proceedings of the acm international symposium on field-programmable gate arrays, FPGA
作者: S. Thakur D.F. Wong Department of Computer Science University of Technology Austin USA
The need for a two-way interaction between logic synthesis and FPGA logic module design has been stressed recently. Having a logic module that can implement many functions is a good idea only if one can also give a sy... 详细信息
来源: 评论