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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Technology mapping for field-programmable gate arrays using integer programming 95

Technology mapping for field-programmable gate arrays using ...

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proceedings of the 1995 IEEE/acm international conference on Computer-aided design

作者： Amit Chowdhary John P. Hayes Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI

ISBN: (纸本)9780818672132

We show that the FPGA technology mapping problem can be efficiently implemented as a mixed integer linear programming (MILP) problem which generates truly optimal mappings. The MILP approach can handle a wide variety of FPGA logic block architectures. We present a compact MILP formulation for logic blocks based on lookup tables (LUTs) multiplexers. We also show that the MILP formulation can be easily modified to modified to optimize area, delay, or a combination of both. We demonstrate that moderately large benchmark circuits can be mapped in a reasonable time using the MILP approach directly. For larger circuits, we propose a technique of partitioning a circuit prior to mapping, which drastically reduces the computation time with little or no loss in optimality.

关键词： field-programmable gate arrays (FPGAs)

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A study of FPGA-based cluster computing by high-speed serial-link communication 8

A study of FPGA-based cluster computing by high-speed serial...

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8th international symposium on Computing and Networking Workshops, CANDARW 2020

作者： Fan, Ruochong Yamaguchi, Yoshiki University of Tsukuba 1-1-1 Ten-ou-dai Tsukuba Ibaraki305-8573 Japan

ISBN: (纸本)9781728199191

With demand growing applications of Big Data and Machine Learning, an enormous amount of computational effort is required in those systems. High-performance computing systems like a data center adopts massively parallel computing that can bring them significant performance improvement. However, it faces making HPC systems based on the same acceleration approach more difficult to achieve further speedup since it generally troubled by its inter-node network due to its latency and insufficient bandwidth. It means this constrains the number of computing nodes in a system, namely system scalability. This article focuses on the flexible and extensible FPGA accelerator, which is widely used in the current supercomputers and data centers. The proposed approach is a communication framework by using an FPGA system with high-speed optical connections which connect among multiple FPGAs. The proposed concept is evaluated on a prototype cluster. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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Fully-Pipelined Architecture for Simulated Annealing-based QUBO Solver on the FPGA 8

Fully-Pipelined Architecture for Simulated Annealing-based Q...

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8th international symposium on Computing and Networking, CANDAR 2020

作者： Kagawa, Hiroshi Ito, Yasuaki Nakano, Koji Yasudo, Ryota Kawamata, Yuya Katsuki, Ryota Tabata, Yusuke Yazane, Takashi Hamano, Kenichiro Graduate School of Advanced Science and Engineering Hiroshima University Kagamiyama 1-4-1 Higashi-Hiroshima739-8527 Japan Research and Development Headquarters NTT DATA Corporation Toyosu Center Bldg Annex 3-9 Toyosu 3-chome Koto-Ku Tokyo135-8671 Japan

ISBN: (纸本)9781728182216

The main contribution of this work is to propose a new fully-pipelined architecture for the QUBO solver on the FPGA. For the fully-pipelined architecture, we propose two local search algorithms based on the simulated annealing with different bit-selection strategies in the local search. The implementation supports a 1024-bit QUBO problem with 16-bit weights. For the problem, we use multiple instances and perform the local search in overlapped execution with pipeline structure. We implemented the proposed circuit on Xilinx UltraScale+ FPGA V09P. The implementation result shows that the circuit can search 3.58 × 1011 solutions per second. In addition, by sharing the block RAM, we implemented a dual annealer architecture that has two QUBO solver into the FPGA. As a result, the dual annealer architecture can search 6.14 × 1011 solutions per second. © 2020 IEEE

关键词： field programmable gate arrays (FPGA)

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An implementation methodology for Neural Network on a Low-end FPGA Board 8

An implementation methodology for Neural Network on a Low-en...

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8th international symposium on Computing and Networking, CANDAR 2020

作者： Wei, Kaijie Honda, Koki Amano, Hideharu Dept. of Information and Computer Science Keio University Yokohama Japan

ISBN: (纸本)9781728182216

Artificial Intelligence(AI) has achieved unprecedented success in various fields including image/speech recognition which is useful for edge computing. Most of AI systems are implemented on power-hungry devices like GPU, high-end FPGA, or even TPU to process data with high performance. However, these energy budgets are often not affordable to edge computing. Low-end FPGA taking advantage of high energy-efficiency is a desirable platform to meet the requirements of image recognition working on small autonomous vehicles. In this paper, we propose the design methodology and implementation to adapt a neural network system to a low-end FPGA board using HLS description. The whole design consists of algorithm-level downscaling and hardware optimization. The former emphasizes the model downscale by considering accuracy. The latter applies various HLS design techniques to speed-up the application running on the target board. In the case study of tiny YOLO (You Only Look Once) v3, the model running on PYNQ-Z1 presents up to 22× acceleration comparing with the PYNQ ARM CPU. Energy efficiency also achieves 3× better than Xeon E5-2667. © 2020 IEEE

关键词： field programmable gate arrays (FPGA)

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An efficient parallel yet pipelined reconfigurable architecture for M-PLN Weightless Neural Networks 14

An efficient parallel yet pipelined reconfigurable architect...

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27th symposium on Integrated Circuits and Systems Design, SBCCI 2014

作者： Da Silva, Felipe P. De Sa, Alan Oliveria Nedjahz, Nadia De Macedo Mourelle, Luiza Postgraduate Program of Electronics Engineering Faculty of Engineering State University of Rio de Janeiro Rio de Janeiro Brazil Dept. of Electronics Engineering and Telecommunications Faculty of Engineering State University of Rio de Janeiro Rio de Janeiro Brazil Brasil PCH Brazil Brazilian Navy Center of Elec-tronics Communications and Information Technology Rio de Janeiro RJ Brazil

ISBN: (纸本)9781479968732

Weightless Neural Networks (WNNs) are a powerful mechanism for pattern recognition. Aiming at enhancing their learning capabilities, Multivalued Probabilistic Logic Neurons (M-PLN) are used, instead of crisp neurons with a 0/1 output. An M-PLN bookkeeps a triggering probability for each input pattern to be recognized. The M-PLN model attempts to strengthen the discrepancies between distinct patterns used during the training process and those that have not yet been processed. In this paper, an efficient yet customizable hardware architecture for M-PLN based WNN is proposed. It implements the structure and learning process of a weightless pyramidal WNN, augmented by a probabilistic rewarding/punishing search algorithm. The training algorithm can adapt itself to the overall hit ratio so far achieved by the network. Using class-dedicated layers, the hardware is able to handle image classification in parallel and thus, very efficiently. Furthermore, the classification process is performed in a pipelined manner so its stages never stop working until all input images are classified. Nonetheless, only one of these layers is active during network training. Last but not least, the architecture is customizable as its structure can be tailored in accordance to the application characteristics. It was modeled and functionally tested. Estimated time requirements based on many simulations are reported. The architecture exhibits performance and reconfiguration capabilities that are very promising and encouraging towards the synthesis of a prototype. © 2014 IEEE.

关键词： field programmable gate arrays (FPGA)

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Future design tools for platform FPGAs 03

Future design tools for platform FPGAs

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symposium on Integrated Circuits and Systems Design (SBCCI)

作者： P. Lysaght Xilinx Research Laboratories CA USA

ISBN: (纸本)9780769520094

According to current projections, programmable platforms will dominate ASIC design starts as the semiconductor industry moves to 90 nm process technology and beyond. In this paper, we assess the implications of this trend and explore the impact it will have on system-level design methodologies for FPGAs. We review current research and practice in system-level design and attempt to assess how much of the ASIC experience will be relevant to future FPGA designers.

关键词： field programmable gate arrays Application specific integrated circuits System-level design Concurrent computing Electronics industry Costs Digital signal processing Embedded software Logic design Silicon

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A Flexible Leakage Trace Collection Setup for Arbitrary Cryptographic IP Cores

A Flexible Leakage Trace Collection Setup for Arbitrary Cryp...

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IEEE international symposium on Hardware Oriented Security and Trust (HOST)

作者： Moschos, Athanassios Fournaris, Apostolos P. Koufopavlou, Odysseas Univ Patras Dept Elect & Comp Engn Rion Campus Patras Greece

ISBN: (纸本)9781538647318

Leakage Assessment and Side Channel Attacks (SCA) leakage trace acquisition tools and platforms require a considerable amount of time to collect millions of traces and rely on custom, hard to change or handle acquisition control mechanisms. To match these problems, in this paper, a flexible and scalable architecture for leakage trace collection is proposed, providing a fast, reconfigurable and flexible control mechanism that can be easily scaled to a wide variety of Devices Under Test (DUT). The proposed system migrates test vector generation, control and transmission, from off-board Personal Computer (PC) to an on-board embedded-system hardware control mechanism. The proposed solution provides a toolset that can be used to structure various leakage assessment scenarios, regardless of the DUT's implemented cryptographic algorithm. The proposed approach enables single, multiple encryption per control loop round and DUT clock frequency adjustment to achieve accurate and fast leakage trace collection even for low-mid range oscilloscopes.

关键词： Cryptography field programmable gate arrays Hardware Computer architecture Software Clocks Process control

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An Accelerated Prototype with Movidius Neural Compute Stick for Real-Time Object Detection 3

An Accelerated Prototype with Movidius Neural Compute Stick ...

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3rd international symposium on Devices, Circuits and Systems, ISDCS 2020

作者： Kaarmukilan, S.P. Hazarika, Anakhi Amal Thomas, K. Poddar, Soumyajit Rahaman, Hafizur Indian Institute of Information Technology Guwahati Dept. of Electronics and Communication Engineering Guwahati India Indian Institute of Engineering Science and Technology Dept.of Information Technology Shibpur India

ISBN: (纸本)9781728165646

Object detection and recognition in realtime is the key task in many computer vision applications such as security surveillance, medical diagnosis, automated vehicle systems, etc. Now-a-days many deep learning techniques, especially convolutional neural networks (CNN) is widely used for real-time image detection and classification. The development of CNN models boosts the accuracy of object detection. However, the complex and data-intensive processing slows down the performance while implemented on hardware. This paper presents a low-powered, portable prototype on Xilinx PYNQ Z2 board with Movidius neural compute stick (NCS) that accelerates the object detection in real-time. Also, the proposed prototype utilized You Only Look Once (YOLO) approach for object detection. Frames per second (FPS), computation time and the probability of object recognition are the parameters considered to evaluate the performance of the proposed prototype and outperform the existing models. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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Heterogeneous resource-elastic scheduling for CPU+FPGA architectures 2019

Heterogeneous resource-elastic scheduling for CPU+FPGA archi...

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10th international symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019

作者： Vaishnav, Anuj Pham, Khoa Dang Koch, Dirk School of Computer Science University of Manchester United Kingdom

ISBN: (纸本)9781450372558

Heterogeneous computing is a key strategy to meet the requirements of many compute-intensive applications. However, currently, CPU+FPGA platforms are commonly underutilized as scheduling is often constrained to a run-to-completion model or acceleration of a single application at a time. To tackle this, this paper proposes heterogeneous resource-elastic scheduling for maximizing the utilization of both CPU and FPGA resources by dynamically scaling the resource allocation for tasks transparently. It achieves this for heterogeneous workloads (OpenCL) by selecting the number of compute units, accelerator type and device types using partial reconfiguration and cooperative fine-grained scheduling to maximize system performance based on runtime conditions. We demonstrate as much as 2× better performance as compared to SDSoC-like platforms and, on average, 20% improvement in performance compared to other standard scheduling algorithms while lowering task wait times. Our results indicate that: 1) workload can be executed seamlessly on both CPU and FPGA without increasing programming effort and 2) co-scheduling applications on heterogeneous systems can improve system performance. © 2019 Copyright held by the owner/author(s). Publication rights licensed to acm.

关键词： field programmable gate arrays (FPGA)

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Are FPGAs suffering from the innovator's dilemna? 13

Are FPGAs suffering from the innovator's dilemna?

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Vaughn Betz Jason Cong University of Toronto Toronto ON Canada UCLA Los Angeles CA USA

ISBN: (纸本)9781450318877

FPGAs constitute a highly profitable industry, with approximately $5 billion of sales per year. High barriers to entry keep most companies away, and enable high profit margins for the incumbents. The industry has grown greatly over the years, but still constitutes a small portion of the overall semiconductor market. This raises the question to be addressed by this panel: is the FPGA community innovating as much as it should, or is a bias to maintain high profit margins and protect the cash flow of the current FPGA market holding us back from exploring new ideas and products that could greatly expand the appeal of and market for FPGA-related technology? This would be a classic case of the innovator's dilemma defined by Clayton Christensen: it is difficult for a company to engage in creative destruction of a cash cow *** distinguished panel of experts will discuss whether we are seeing major innovation in architectures, design flows and applications, or only incremental improvements. We will also discuss if any new (possibly low margin) application domain is left out by the FPGA industry, what radical ideas should be explored, and whether large incumbents, new startups, academia or some combination are best able to attack these new areas.

关键词： field programmable gate arrays

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