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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 834 条记录，以下是761-770 订阅

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Diagnosing programmable interconnect systems for FPGAs 96

Diagnosing programmable interconnect systems for FPGAs

引用

proceedings of the 1996 acm fourth international symposium on field-programmable gate arrays

作者： Fabrizio Lombardi David Ashen Xiaotao Chen Wei Kang Huang Department of Computer Science Texas A&M University College Station TX Dept. of Electronic Engineering Fudan University Shanghai 200433 P.R. China

No abstract available.

ISBN: (纸本)9780897917735

No abstract available.

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Unleashing the Power of FPGAs as programmable Switches 20

Unleashing the Power of FPGAs as Programmable Switches

引用

proceedings of the 2020 acm/sigda international symposium on field-programmable gate arrays

作者： Thomas Luinaud Thibaut Stimpfling Jeferson Santiago Da Silva Yvon Savaria J.M. Pierre Langlois Polytechnique Montréal Montréal PQ Canada Polytechnique Montréal Montreal PQ Canada Polytechnique Montréal Montréal Canada

ISBN: (纸本)9781450370998

The P4 language and the PISA architecture have revolutionized the field of networking. Thanks to P4 and PISA, new networking applications and protocols can be rapidly evaluated on high performance switches. While P4 allows the expression of a wide range of packet processing algorithms, current programmable switch architecture limit the overall processing flexibility. To address this shortcoming recent work have proposed to implement PISA on FPGAs. However, little effort has been devoted to analyze whether FPGAs are good candidates to implement PISA. In this work, we take a step back and evaluate the micro-architecture efficiency of various PISA blocks. Using a theoretical analysis and experiments, we demonstrate that current FPGA architecture drastically limit the performance of a few PISA blocks. Thus, we explore two avenues to alleviate these shortcomings. First, we identify some network applications that are well tailored to current FPGAs. Second, to support a wider range of networking applications, we propose modifications to the FPGA architecture which can also be of interest outside the networking field.

关键词： data plane network p4

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[email protected] all-programmable SoC ecosystem 14

[email protected] all-programmable SoC ecosystem

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proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Antonio Filgueras Eduard Gil Daniel Jimenez-Gonzalez Carlos Alvarez Xavier Martorell Jan Langer Juanjo Noguera Kees Vissers Barcelona Supercomputing Center - BSC-CNS Barcelona Spain Universitat Politecnica de Catalunya - UPC Barcelona Spain Xilinx Inc. Dublin Ireland Xilinx inc. San Jose CA USA

ISBN: (纸本)9781450326711

OmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely influenced the recently appeared OpenMP 4.0 specification. Zynq All-programmable SoC combines the features of a SMP and a FPGA and benefits DLP, ILP and TLP parallelisms in order to efficiently exploit the new technology improvements and chip resource capacities. In this paper, we focus on programmability and heterogeneous execution support, presenting a successful combination of the OmpSs programming model and the Zynq All-programmable SoC platforms.

关键词： task dataflow models automatic hardware generation framework heterogenous parallel programming model

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DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only) 18

DATuner: An Extensible Distributed Autotuning Framework for ...

引用

proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Gai Liu Ecenur Ustun Shaojie Xiang Chang Xu Guojie Luo Zhiru Zhang Cornell University Ithaca NY USA IBM Research China Beijing China Peking University Beijing China

ISBN: (纸本)9781450356145

Mainstream FPGA tools contain an extensive set of user-controlled compilation options and internal optimization strategies that significantly impact the design quality. These compilation and optimization parameters create a complex design space that human designers may not be able to effectively explore in a time-efficient manner. In this work we describe DATuner, an open-source extensible distributed autotuning framework for optimizing FPGA designs and design automation tools using an ensemble of search techniques managed by multi-armed bandit algorithms. DATuner is designed for a distributed environment that uses parallel searches to amortize the significant runtime overhead of the CAD tools. DATuner provides convenient interface for extension to user-supplied tools, which enables the end users to apply DATuner to design tools/flows of their interest. We demonstrate the effectiveness and extensibility of DATuner using three case studies, which include clock frequency optimization for FPGA compilation, fixed-point optimization, and autotuning logic synthesis transformations.

关键词： field-programmable gate array design automation distributed autotuning

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Sparse Winograd Convolutional Neural Networks on Small-scale Systolic arrays 19

Sparse Winograd Convolutional Neural Networks on Small-scale...

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proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Feng Shi Haochen Li Yuhe Gao Benjamin Kuschner Song-Chun Zhu University of California Los Angeles Los Angeles CA USA University of Hong Kong Hong Kong China

ISBN: (纸本)9781450361378

The reconfigurability, energy-efficiency, and massive parallelism on FPGAs make them one of the best choices for implementing efficient deep learning accelerators. However, state-of-art implementations seldom consider the balance between high throughput of computation power and the ability of the memory subsystem to support it. In this paper, we implement a framework on FPGA by combining the sparse Winograd convolution, clusters of small-scale systolic arrays, and a tailored recursive Z-Morton memory layout design. We also provide an analytical model analysis for the general Winograd convolution algorithm as a design reference. Experimental results on various CNN models show that it achieves very high computation resource utilization, 20x~30x energy efficiency, and more than 5x speedup compared with the dense implementation.

关键词： systolic arrays convolutional neural networks sparse matrix multiplication fpga winograd transform

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Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system 8

Horizontal division of deep learning applications with all-t...

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8th international symposium on Computing and Networking Workshops, CANDARW 2020

作者： Yamauchi, Yugo Ahmed, Akram Ben Hironaka, Kazuei Iizuka, Kensuke Amano, Hideharu Keio University 3-14-1 Hiyoshi Yokohama223-8522 Japan

ISBN: (纸本)9781728199191

Although convolutional neural networks (CNNs) have plenty of parallelism, traditional layer-by-layer task division designs for multi-FPGA systems have the following problems: (1) The computational load of each layer is different from each other, so the execution time is dominated with the heaviest one. (2) Each FPGA must be designed independently, it means that we must design, generate and manage various configuration files. To address this problem, we propose a horizontal division method that enables us to use of a single design for each FPGA. All layers are divided horizontal direction of the target CNN, and a set of layers is implemented on an FPGA. It reduces the time of design as well as management costs for the execution. Also, since the weight data can be separated, the usage of local memory can be reduced. The apparent disadvantage of this method is that it requires all-to-all data communication between FPGA boards, and so it is not suitable to traditional multi-FPGA systems with a simple linear network. Here, we tried to apply the method to FiC (Flow-in-Cloud) which has a powerful network to enable efficient broadcasting. A simple CNN LeNet and a matrix multiplication for more practical fully connected layer is implemented on the FiC prototype. As a result of the evaluation, LeNet using 8 FP-GAs achieved 7.5 times faster than that with a single FPGA, and achieved 12.6 times faster than the optimized software of a high-end CPU. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays 98

SMAP: heterogeneous technology mapping for area reduction in...

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proceedings of the 1998 acm/sigda sixth international symposium on field programmable gate arrays

作者： Steven J. E. Wilton Department of Electrical and Computer Engineering University of British Columbia Vancouver BC Canada V6T 1Z4

ISBN: (纸本)9780897919784

It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for customers that do not use all of the storage provided. This chip area need not be wasted, and can in fact be used very efficiently, if the arrays are configured as large multi-output ROMs, and used to implement *** order to efficiently use the embedded arrays in this way, a technology mapping algorithm that identifies parts of circuits that can be efficiently mapped to an embedded array is required. In this paper, we describe such an algorithm. The new tool, called SMAP, packs as much circuit information as possible into the available memory arrays, and maps the rest of the circuit into four-input lookup-tables. On a set of 29 sequential and combinational benchmarks, the tool is able to map, on average, 60 4-LUTs into a single 2-Kbit memory array. If there are 16 arrays available, it can map, on average, 358 4-LUTs to the 16 arrays.

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FPGA-based fine-grain parallel computing (abstract only) 11

FPGA-based fine-grain parallel computing (abstract only)

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Andrew W. Hill Andrea Di Blas Richard Hughey University of California Santa Cruz Santa Cruz CA USA

ISBN: (纸本)9781450305549

FPGAs are increasing in computing power at a significant rate while the non-recurring engineering costs and time-to-market remain significant lower than those for application-specific integrated circuits (ASICs), encouraging FPGAs to be used in areas previous dominated by ASICs. In this study, we examine the appropriateness of FPGAs for high-performance, low-volume prodution parallel computing by mapping an existing ASIC-based massively parallel single-instruction, multiple data (SIMD) computer, the UCSC Kestrel, to a variety of FPGAs. The design has a raw peak performance of over 187 billion 8-bit operations per second (OPS), 48 times faster than the original ASIC-based Kestrel, using a Xilinx Virtex-6, and a cost efficiency of up to 81 MOPS/$ using a Xilinx Spartan-3. We also show that we can implement the entire original Kestrel (512 processing elements) as a system on a single programmable chip.

关键词： system on a programmable chip simd parallel computing

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From high-level deep neural models to FPGAS 49

From high-level deep neural models to FPGAS

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49th Annual IEEE/acm international symposium on Microarchitecture, MICRO 2016

作者： Sharma, Hardik Park, Jongse Mahajan, Divya Amaro, Emmanuel Kim, Joon Kyung Shao, Chenkai Mishra, Asit Esmaeilzadeh, Hadi Lab School of Computer Science Georgia Institute of Technology United States Intel Corporation United States

ISBN: (纸本)9781509035083

Deep Neural Networks (DNNs) are compute-intensive learning models with growing applicability in a wide range of domains. FPGAS are an attractive choice for DNNs since they offer a programmable substrate for acceleration and are becoming available across different market segments. However, obtaining both performance and energy efficiency with FPGAS is a laborious task even for expert hardware designers. Furthermore, the large memory footprint of DNNs, coupled with the FPGAS' limited on-chip storage makes DNN acceleration using FPGAS more challenging. This work tackles these challenges by devising DnnWeaver, a framework that automatically generates a synthesizable accelerator for a given (DNN, FPGA) pair from a high-level specification in Caffe [1]. To achieve large benefits while preserving automation, DNNWEAVER generates accelerators using hand-optimized design templates. First, DnnWeaver translates a given high-level DNN specification to its novel ISA that represents a macro dataflow graph of the DNN. The DnnWeaver compiler is equipped with our optimization algorithm that tiles, schedules, and batches DNN operations to maximize data reuse and best utilize target FPGA's memory and other resources. The final result is a custom synthesizable accelerator that best matches the needs of the DNN while providing high performance and efficiency gains for the target FPGA. We use DnnWeaver to generate accelerators for a set of eight different DNN models and three different FPGAS, Xilinx Zynq, Altera Stratix V, and Altera Arria 10. We use hardware measurements to compare the generated accelerators to both multicore CPUs (ARM Cortex A15 and Xeon E3) and many-core GPUs (Tegra K1, GTX 650Ti, and Tesla K40). In comparison, the generated accelerators deliver superior performance and efficiency without requiring the programmers to participate in the arduous task of hardware design. © 2016 IEEE.

关键词： field programmable gate arrays (FPGA)

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The design of RPM: an FPGA-based multiprocessor emulator 95

The design of RPM: an FPGA-based multiprocessor emulator

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proceedings of the 1995 acm third international symposium on field-programmable gate arrays

作者： Koray Öner Luiz A. Barroso Sasan Iman Jaeheon Jeong Krishnan Ramamurthy Michel Dubois Department of Electrical Engineering - Systems University of Southern California Los Angeles CA

ISBN: (纸本)9780897917438

Recent advances in field-programmable gate arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improvements in Computer-Aided Design (CAD) tools, mainly in synthesis tools, greatly simplify the design of large circuits. The RPM (Rapid Prototype Engine for Multiprocessors) Project leverages these two technological advances. Its goal is to develop a common hardware platform for the emulation of multiprocessor systems with different *** cost reasons, the use of FPGAs in RPM is limited to the memory controllers, while the rest of the emulator, including the processors, memories and interconnect, is built with off-the-shelf components. A flexible non-intrusive event logging mechanism is included at all levels of the memory hierarchy, making it possible to monitor the emulation in very fine detail. This paper presents the hardware design of RPM.

关键词： rapid prototyping field-programmable gate arrays shared-memory multiprocessors logic emulation message-passing multicomputers

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