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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only) 10

Design space exploration of throughput-optimized arrays from...

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proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Arpith C. Jacob Jeremy D. Buhler Roger D. Chamberlain Washington University in St. Louis St. Louis MO USA

ISBN: (纸本)9781605589114

Many compute-bound software applications have seen order-of-magnitude speedups using application-specific accelerators built on specialized architectures such as field-programmable gate arrays. These architectures are particularly good at implementing systems of recurrence equations realized as systolic arrays. We pursue high-level synthesis tools for recurrence equations that can search the space of possible parallel array designs to optimize various design criteria. Most existing approaches produce an array that is latency-space optimal. We target applications that operate on a large collection of small inputs, e.g. a database of biological sequences. For these applications, overall throughput, rather than latency per input, is the most important measure of *** this work we introduce a new design space exploration procedure to optimize throughput of a systolic array subject to area and bandwidth constraints of an FPGA device. We show that the throughput of an array is dependent on the maximum number of lattice points executed by any processor in the array, which is determined solely by the array's projection vector. We describe a bounded search process to find throughput-optimized projection vectors, discovering a range of array designs that are optimal for inputs of various *** have written a tool in C++ that accepts recurrence descriptions and produces throughput-optimized array mappings. We have applied our technique to the banded Smith-Waterman and Nussinov RNA folding algorithms, and present novel arrays that are 4-33x and 2-14x faster, respectively, than the currently-used latency-optimized array.

关键词： dynamic programming systolic array throughput optimization fpga recurrences

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Architecture and routability analysis for row-based FPGAs 93

Architecture and routability analysis for row-based FPGAs

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IEEE international Conference on Computer-Aided Design

作者： M. Pedram B.S. Nobandegani B.T. Preas Department of EE-Systems University of Southern California Los Angeles CA USA Computer Science Laboratory Xerox Palo Alto Research Center Palo Alto CA USA

ISBN: (纸本)9780818644900

FPGAs combine the logic integration benefits of custom VLSI with the design, production, and time-to-market advantages of standard logic ICs. One class of FPGAs has rows of logic cells interspersed with routing channels have given this family of FPGA devices the flavor of traditional channeled gate arrays or standard cells. This class has the flavor of traditional channeled gate arrays or standard cells and is exemplified by the Actel family of FPGAs. However, unlike conventional standard cell designs, the FPGA routing channels contain predefined wiring segments of various lengths which may be interconnected using antifuses. This paper develops analytical models that permit the design of FPGA routing channels and the analysis of the routability of row-based FPGAs devices based on a generic characterization of the row-based FPGA routing algorithms. In particular, it demonstrates that (using probabilistic models for the origination point and length for connections) an FPGA with properly designed segment length and distribution can be nearly as efficient as a mask-programmable channel (in terms of number of tracks required for routing a given interconnection specification). Experimental results corroborate this prediction. In addition, this paper provides a method for evaluating various channel architectures.

关键词： field programmable gate arrays Logic devices Routing Logic design Logic arrays Algorithm design and analysis Very large scale integration Production Time to market Wiring

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The Brain Memory Architecture HW/SW Co-Design Platform with Adaptive CNN Algorithm

The Brain Memory Architecture HW/SW Co-Design Platform with ...

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2020 international Computer symposium, ICS 2020

作者： Chiu, Jih-Ching Wang, Yu-Yi Lin, Wei-Yi National Sun Yat-sen University Department of Electrical Engineering Kaohsiung Taiwan

ISBN: (纸本)9781728192550

As the demand for machine learning, edge computing, and the Internet of Things technology increases, computing efficiency and energy consumption has become an important basis for computing choices. Although the graphics processing unit(GPU) has a high degree of parallel computing capability, its energy consumption is large, and the data transmission is limited by the system bus bandwidth. Therefore, our laboratory previously proposed the Brain Memory Architecture prototype architecture, which integrates FPGA and memory as a computing architecture, which has the advantages of high-efficiency, and low-power computing and does not require data exchange through the system bus. Based on this prototype architecture, this paper constructs the Brain Memory Architecture HW/SW Co-Design Platform (BMCD platform) to provide a good user interface so that users can easily build a hardware and software collaborative design computing environment. Through the library provided by the platform to establish the data transmission and calculation between acceleration hardware and memory to solve the bandwidth limitation of the traditional system bus. In this platform, the AXI4-stream interconnect core is provided as a standard interface for data handshaking with acceleration hardware, which reduces user design complexity and maintains the scalability of connection with other computing IP cores. In platform evaluation, design and adaptive CNN algorithm for hardware and software design platform, provide data quantization methods to reduce data bits to reduce the required data bandwidth and storage space and propose a dynamic adjustment algorithm for integer and decimal ratios to correct the accuracy and design problems that may be caused by data quantization. With this adaptive CNN algorithm architecture and BMCD platform to construct a rapid data transmission. This paper finally analyzes the comparison of the weight transmission time of different CNN models with the CPU and the GPU. The m

关键词： field programmable gate arrays (FPGA)

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Exploiting temporal parallelism in particle-based incompressive fluid simulation on FPGA 8

Exploiting temporal parallelism in particle-based incompress...

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8th international symposium on Computing and Networking, CANDAR 2020

作者： Orsztynowicz, Manfred Amano, Hideharu Kubota, Kenichi Miyajima, Takaaki Faculty of Science and Technology Keio University YokohamaKanagawa Japan Aeronautical Technology Directorate Japan Aerospace Exploration Agency Chofu Tokyo Japan Center for Computational Science RIKEN Kobe Hyogo Japan

ISBN: (纸本)9781728182216

—While the semiconductor manufacturing process is shrinking, the Bytes per Flop (B/F) ratio on recent machines is becoming lower. Particle-based computational fluid dynamics (CFD) methods such as Moving Particle Simulation (MPS) require a higher B/F ratio than that of stencil-based CFD methods. Techniques to reduce the B/F ratio by exploiting temporal parallelism is becoming popular in stencil-based CFD methods on CPU and GPU. It is also reported that a technique to combine temporal blocking with stencil buffer is suitable for FPGA and can outperform CPU and GPU. On the other hand, it has been considered that temporal parallelism cannot be exploited in the particle-based CFD methods. This is because the number of particles in each bucket, a three-dimensional grid covering a computational domain, changes every time-step. In this paper, we propose a technique to exploit temporal parallelism in MPS method, a particle-based CFD method for incompressive fluid. The key idea is that the buckets in MPS can be considered as stencils in stencil-based CFD. This is because the maximum number of particles in a bucket can be assumed empirically in the case of an incompressible fluid. To the best of our knowledge, this is the first research which exploits temporal parallelism in the particle-based incompressible fluid method. We implemented the proposed technique with a degree of temporal parallelism of three. We also optimized it on Intel Arria10 FPGA in Intel HLS, and measured the performance and resource consumption. The result shows that the optimized implementation with a degree of temporal parallelism of three achieved 2.1 times speedup compared with implementation without exploiting temporal parallelism on CPU. © 2020 IEEE

关键词： field programmable gate arrays (FPGA)

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Design and Implementation of a Primary Visual Cortex Pathway Model Based on Opponent-process Theory 24

Design and Implementation of a Primary Visual Cortex Pathway...

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proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Hui Wei Jingyong Ye Yutong Chen Heng Wu Fudan University Shanghai China University of Science and Technology of China Hefei China

ISBN: (纸本)9798400704185

Neurobiology has made groundbreaking discoveries that have propelled the development of brain-inspired computing. This new field of research has led to the creation of neural pathways that mirror the human brain's visual system, providing numerous transformative insights for modern image processing. Brain-like vision offers remarkable processing efficiency and promises a range of exciting applications, from enhancing video surveillance to improving medical diagnosis. However, current brain-inspired computing models lack portability and efficient power consumption, which limits their widespread use. To address these challenges, we've designed a brain-like color opponent multi-layer neural network model on field programmable gate arrays (FPGAs). This innovative approach enhances portability, reduces power consumption, and increases parallelism in the brain-like computational model. We've conducted rigorous experiments on natural images, and the results are promising. FPGAs can further enhance this innovative approach by improving computational parallelism and enhancing the display of crucial structural information while downplaying trivial details. This integration of biological mechanisms into practical embedded systems is a significant step towards merging these two technologies. Our multi-layer neural network structure aligns with FPGAs' in-memory computing mechanism, bridging the gap between these two technologies. Our work represents a step towards merging them and utilizes physiological color opponent theory to enhance FPGAs' effectiveness in practical image processing applications. By combining the power of neurobiology with the flexibility of FPGAs, we can create more efficient and practical solutions for image processing tasks in various fields.

关键词： brain-like vision neurovisual pathways opponent-process programmable devices

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A timing driven N-way chip and multi-chip partitioner 93

A timing driven N-way chip and multi-chip partitioner

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IEEE international Conference on Computer-Aided Design

作者： K. Roy C. Sechen Department of Electrical Engineering University of Washington Seattle WA USA

ISBN: (纸本)9780818644900

With the growing complexity of integrated circuits and the advent of new technologies and new generations of packaging technologies, an essential physical design tool is a flexible physical partitioner. We therefore present a timing driven n-way chip and multi-chip partitioner which we call Tomus. The partitioner enables an automatic layout package to (1) divide and conquer the physical design process of field programmable gate array (FPGA) circuits or mixed macro/standard cell circuits and (2) physically partition a circuit onto n chips for a multichip package. Using a two-phased natural and adaptive clustering method, the annealing-based N-way partitioner executes four to 22 times faster with improved partitioning results. The placement results for industrial FPGAs were improved by 90% over the only available industrial placement tool. Our partitioner outperformed an industrial FPGA partitioner by 95% in MCM partitioning.

关键词： Timing field programmable gate arrays Integrated circuit technology Integrated circuit packaging Wire Automatic control Partitioning algorithms Computational modeling Simulated annealing Process design

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FiT: An Automated Toolkit for Matching Processor Architecture to Applications (Abstract Only) 15

FiT: An Automated Toolkit for Matching Processor Architectur...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Charles Mutigwe Johnson Kinyua Farhad Aghdasi NxCORES Research East Longmeadow MA USA Virginia International University Fairfax VA USA University of Fort Hare Alice South Africa

ISBN: (纸本)9781450333153

As the complexity of designing electronic systems continues to grow, the most commonly used solution has been to move the design process to higher levels of abstraction via software tools. In this work we present one such tool that can be used to automatically generate custom processors and systems-on-chip (SoC) from C source code or application binary files, with no requirement for the user to understand any of the underlying hardware systems. This tool also does not call for the application to be profiled for any 'hot spots' as a prerequisite for generating the custom processor. We use the toolkit to generate two types of custom processors; the area-optimized processors and the performance-optimized processors. We study the resource utilization of the custom processors and compare them with those predicted by the core density model. We find that the performance-optimized processor results are as predicted by the core density model.

关键词： electronic system level (esl) design application-specific soft processor reconfigurable computing c-to-silicon compiler

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Power-aware FPGA technology mapping for programmable-VT architectures (abstract only) 12

Power-aware FPGA technology mapping for programmable-VT arch...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Wei Ting Loke Yajun Ha Xilinx Asia Pacific Pte. Ltd. & National University of Singapore Singapore Singapore National University of Singapore Singapore Singapore

ISBN: (纸本)9781450311557

In this paper, we present a framework for leakage power reduction in FPGAs with programmable-VT architectures, with focus on dual-VT technology mapping. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the possible strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. FPGAs with the ability to tune LUT VT via RBB offer the potential of reducing leakage power with no sacrifice to circuit speed. Today, Altera's Stratix line of FPGAs oer some levels of VT programmability, but with optimizations limited to the post-P&R stage. We present a novel technology mapper (RBBMap), logic block packer (RBBPack) and placement-and-routing tool (RBBVPR) that together demonstrate the advantages in moving RBB optimizations upwards to the technology mapping level. Compared to an existing power-optimized technology mapping tool Emap, our framework oers an average of 44.41% savings in average logic block leakage power and 30.88% savings in average total energy consumption. We also illustrate why our work is potentially superior to another comparable work DVMap-2 that utilizes a dual-VDD approach.

关键词： fpga multiple voltage programmable-vt dual-vt reverse back bias technology mapping

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A field programmable array core for image processing (abstract only) 12

A field programmable array core for image processing (abstra...

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Declan Walsh Piotr Dudek The University of Manchester Manchester United Kingdom

ISBN: (纸本)9781450311557

Massively parallel processor arrays have been shown to be an effective and suitable choice for image processing tasks [1]. More recently, some of the state of the art processor arrays have been used for real-time machine vision tasks such as intelligent transport system applications [2] or video processing on mobile applications [3] providing a much more powerful solution than a conventional processor. A number of Single Instruction Multiple Data (SIMD) processor arrays have been implemented on FPGAs [4]-[6], which are particularly suited to implementing such processor architectures because of their similarities of both being arrays of fine grained logic elements. In this work, we propose an FPGA implementation of a processor array where the processing elements (PEs) are as small as possible, while providing local memory sufficient for processing greyscale images. The PE is then replicated to form an array. A 32 × 32 PE array is implemented on a Xilinx Virtex 5 XC5VLX50 FPGA using the four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 96 MHz and executes a peak of 98.3 giga operations per second (GOPS) (bit-serial operations). A binary edge detection algorithm is performed in 52.08 ns. Uploading and downloading a binary image in a 32 × 32 array takes an extra 687.5 ns. Sobel edge detection of an 8-bit greyscale image is performed in 5.33 µs. Uploading and downloading an 8-bit greyscale image in a 32 × 32 array takes 5.36 µs. With larger FPGAs being available in the future, the array sizes comparable to state of the art custom designed ICs can be implemented on these FPGAs.

关键词： architecture fpga simd image processor array

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ReCoNet: modeling and implementation of fault tolerant distributed reconfigurable hardware 03

ReCoNet: modeling and implementation of fault tolerant distr...

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symposium on Integrated Circuits and Systems Design (SBCCI)

作者： C. Haubelt D. Koch J. Teich Department of Computer Science 12 University of Erlangen Nuremberg Germany

ISBN: (纸本)9780769520094

Recent research was mainly focused on the OS support for a single reconfigurable chip. This paper presents a general approach to manage fault tolerant distributed reconfigurable hardware. In order to run such a system, three basic tasks must be implemented: (i) rerouting to compensate line errors, (ii) rebinding to compensate node failures, and (iii) hardware reconfiguration to allow the optimization of these systems during runtime. This paper proposes first ideas and solutions of these management functions. Furthermore, a prototype implementation consisting of four fully connected FPGAs is presented.

关键词： Fault tolerance Hardware field programmable gate arrays Prototypes Energy consumption Delay Computer science Operating systems Automotive engineering Body area networks

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