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检索条件"任意字段=Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 834 条记录，以下是71-80 订阅

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Evaluation of low-leakage design techniques for field programmable gate arrays

Evaluation of low-leakage design techniques for field progra...

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acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Rahman, Arifur Polavarapuv, Vijay Department of Electrical Engineering Polytechnic University Brooklyn NY 11201 United States

In this paper we evaluate the trade-offs between various low-leakage design techniques for field programmable gate arrays (FGPAs) in deep sub-micron technologies. Since multiplexers are widely used in FPGAs for implementing look up tables (LUTs) and connection and routing switches, several low-leakage implementations of pass transistor based multiplexers and routing switches are proposed and their design trade-offs are presented based on transistor-level simulation, physical design, and impact on overall system performance. We find that gate biasing, the use of redundant SRAM cells, and integration of multi-Vt technology are ideal for FPGAs, and they can reduce leakage current by 2X-4X compared to an implementation without any leakage reduction technique. For some of the potential low-leakage design techniques being evaluated in our study, the impact on chip area is very minimal to an increase of 15% - 30%.

关键词： field programmable gate arrays

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Architectural Improvements for field programmable Counter arrays: Enabling Efficient Synthesis of Fast Compressor Trees on FPGAs 08

Architectural Improvements for Field Programmable Counter Ar...

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16th acm/sigda international symposium on field-programmable gate arrays

作者： Cevrero, Alessandro Athanasopoulos, Panagiotis Parandeh-Afshar, Hadi Verma, Ajay K. Brisk, Philip Gurkaynak, Frank K. Leblebici, Yusuf Ienne, Paolo Ecole Polytech Fed Lausanne Inst Microelect & Microsyst Microelect Syst Lab CH-1015 Lausanne Switzerland

ISBN: (纸本)9781595939340

The field programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addition and multiplication operations into large multi-input addition operations, which are synthesized as compressor trees on the FPCA;the remaining portion of the circuit is synthesized on the FPGA. This paper presents a series of architectural improvements to the FPCA that reduce routing delay, increase flexibility and component utilization, and simplify the integration process. Using an FPGA containing six FPCAs, we observed average and maximum speedups of 1.60x and 2.40x on a set of arithmetic benchmarks.

关键词： FPGA field programmable Counter Array (FPCA)

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Coarse-grained FPGA architecture for high-performance FIR filtering

Coarse-grained FPGA architecture for high-performance FIR fi...

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Anderson, James R. Sheth, Siddharth Roy, Kaushik Intel Corp Santa Clara United States

This paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar to that of a custom ASIC design, while allowing all of the basic FIR design parameters, including coefficient precision, to be configured. Previous research has already shown that FPGAs can provide a high-performance alternative to DSP processors. Experimental comparisons in this paper show that the performance and area efficiency of the proposed architecture is similar to that of custom approaches across a wide range of filter sizes and configurations.

关键词： field programmable gate arrays

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Design and implementation of a field programmable analogue array 96

Design and implementation of a field programmable analogue a...

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proceedings of the 1996 acm/sigda international symposium on field programmable gate arrays

作者： Bratt, Adrian Macbeth, Ian Cheshire United Kingdom

ISBN: (纸本)9780897917735

A field programmable Analogue Array (FPAA) is presented based on switched capacitor technology. The chip allows true array programming of undedicated analogue cells. There is provision for internal signal-conditional switching as part of the normal function of the array. With the presented chip it is possible to implement a very wide range of analogue signal processing functions such as data conversion, linear signal processing and non-linear functions. These functional configurations can be reconfigured and parameterised on the fly during concurrent signal processing. Very rapid prototyping of switched capacitor circuits is facilitated. The field programmable nature of the chip allows several markets/customers to be targeted simultaneously with obvious benefits in terms of both volume of sales and reduced time to market.

关键词： Linear integrated circuits

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Eliminating the Memory Bottleneck: An FPGA-based Solution for 3D Reverse Time Migration 11

Eliminating the Memory Bottleneck: An FPGA-based Solution fo...

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19th Annual acm international symposium on field-programmable gate arrays

作者： Fu, Haohuan Clapp, Robert G. Tsinghua Univ Ctr Earth Syst Sci Beijing 100084 Peoples R China

ISBN: (纸本)9781450305549

Memory-related constraints (memory bandwidth, cache size) are nowadays the performance bottleneck of most computational applications. Especially in the scenario of multiple cores, the performance does not scale with the number of cores in many cases. In our work, we present our FPGA-based solution for the 3D Reverse Time Migration (RTM) algorithm. As the most computationally demanding imaging algorithm in current oil and gas exploration, RIM involves various computational challenges, such as a high demand for storage size and bandwidth, and a poor cache behavior. Combining optimizations from both the algorithmic and architectural perspectives, our FPGA-based solution manages to remove the memory constraints and provide a high performance that can scale well with the amount of computational resources available. Compared with an optimized CPU implementation using two quad-core Intel Nehalem CPUs, our solution achieves 4x speedup on two Virtex-5 FPGAs, and 8x speedup on two Virtex-6 FPGAs. Our projection demonstrates that the performance will continue to scale with the future increase of FPGA capacities.

关键词： field programmable gate arrays (FPGA) Reverse Time Migration (RTM)

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Improving bitstream compression by modifying FPGA architecture 13

Improving bitstream compression by modifying FPGA architectu...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Razavi, Seyyed Ahmad Saheb Zamani, Morteza Department of Computer Engineering and Information Technology Amirkabir University of Technology Tehran Iran

ISBN: (纸本)9781450318877

The size of configuration bitstreams of field-programmable gate arrays (FPGA) is increasing rapidly. Compression techniques are used to decrease the size of bitstreams. In this paper, an appropriate bitstream format and variable symbol lengths are proposed to utilize the routing patterns for enhancing the compression efficiency. An order of inputs of multiplexers in switch modules is also proposed to improve the symbol statistics and hence, the compression efficiency. A framework to generate the bitstream and hardware description of FPGAs is developed as well. Experimental results over 20 MCNC benchmarks show that by applying the proposed approaches, the compression rate is improved by 46% on average compared to the methods with fixed symbol lengths without any area and performance degradation. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in FPGAs 12

Reducing the Cost of Floating-Point Mantissa Alignment and N...

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20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Moctar, Yehdhih Ould Mohammed George, Nithin Parandeh-Afshar, Hadi Ienne, Paolo Lemieux, Guy G. F. Brisk, Philip Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781450311557

In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemented using several rows of small multiplexers;unfortunately, multiplexer-based logic structures map poorly onto LUTs. FPGAs, meanwhile, contain a large number of multiplexers in the programmable routing network;these multiplexer are placed under static control of the FPGA's configuration bitstream. In this work, we modify some of the routing multiplexers in the intra-cluster routing network of a CLB in an FPGA to implement shifters for floating-point mantissa alignment and normalization;the number of CLBs required for these operations is reduced by 67%. If shifting is not required, the routing multiplexers that have been modified can be configured to operate as normal routing multiplexers, so no functionality is sacrificed. The area overhead incurred by these modifications is small, and there is no need to modify every routing multiplexer in the FPGA. Experiments show that there is no negative impact in terms of clock frequency or routability for benchmarks that do not use the dynamic multiplexers.

关键词： field programmable gate Array (FPGA) Floating-point Mantissa Alignment Normalization

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Towards Agile DNN Accelerator Design Using Incremental Synthesis on FPGAs 22

Towards Agile DNN Accelerator Design Using Incremental Synth...

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Xiao, Qingcheng Liang, Yun Peking University Beijing China

ISBN: (纸本)9781450391498

Hardware-software co-design is the new trend for deep neural network and FPGA accelerator development, which iteratively revises and tunes the full system. The bottleneck of the approach lies in the time-consuming hardware synthesis. In this paper, we propose an incremental synthesis framework Acoda to rapidly design DNN accelerators on FPGAs. Based on the observation that most revisions to DNNs are minor and local, Acoda reuses existing hardware modules and incrementally modifies the accelerator. It first detects the software revisions using a graph edit distance algorithm. Then, it maps the software revisions to hardware revisions through a multi-level reuse hierarchy. As a result, Acoda speeds up the design process by 9.31X to 34.17X and achieves performance results comparable to off-the-shelf accelerators. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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A pipelined configurable gate array for embedded processors

A pipelined configurable gate array for embedded processors

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Lodi, Andrea Toma, Mario Campi, Fabio ARCES University of Bologna Bologna Italy

In recent years the challenge of high performance, low power retargettable embedded system has been faced with different technological and architectural solutions. In this paper we present a new configurable unit explicitly designed to implement additional reconfigurable pipelined datapaths, suitable for the design of reconfigurable processors. A VLIW reconfigurable processor has been implemented on silicon in a standard 0.18 μm CMOS technology to prove the effectiveness of the proposed unit. Testing on a signal processing algorithms benchmark showed speedups from 4.3x to 13.5x and energy consumption reduction up to 92%.

关键词： field programmable gate arrays

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Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic 02

Efficient architectures for implementing montgomery modular ...

引用

FPGA 2002: Tenth acm international symposium on field-programmable gate arrays

作者： Daly, Alan Marnane, William Dept. of Elec. and Electronic Eng. University College Cork Cork Ireland

ISBN: (纸本)9781581134520

This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on FPGA (field programmable gate Array). Some new architectures are presented, including a pipelined architecture exploiting the maximum carry chain length of the FPGA which is used to implement the modular exponentiation operation required for RSA encryption and decryption. Speed and area comparisons are performed on the optimised designs. The issues of targeting a design specifically for a reconfigurable device are considered, taking into account the underlying architecture imposed by the target technology.

关键词： field programmable gate arrays

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