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Architecture of centralized field-configurable memory 95

Architecture of centralized field-configurable memory

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proceedings of the 1995 acm third international symposium on field-programmable gate arrays

作者： Steven J. E. Wilton Jonathan Rose Zvonko G. Vranesic Department of Electrical and Computer Engineering University of Toronto Toronto Ontario Canada M5S 1A4

ISBN: (纸本)9780897917438

As the capacities of FPGAs grow, it becomes feasible to implement the memory portions of systems directly on an FPGA together with logic. We believe that such an FPGA must contain specialized architectural support in order to implement memories efficiently. The key feature of such architectural support is that it must be flexible enough to accommodate many different memory shapes (widths and depths) as well as allowing different numbers of independently-addressed memory blocks. This paper describes a family of centralized field-Configurable Memory architectures which consist of a number of memory arrays and dedicated mapping blocks to combine these arrays. We also present a method for comparing these architectures, and use this method to examine the tradeoffs involved in choosing the array size and mapping block capabilities.

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HGA: a hardware-based genetic algorithm 95

HGA: a hardware-based genetic algorithm

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proceedings of the 1995 acm third international symposium on field-programmable gate arrays

作者： Stephen D. Scott Ashok Samal Shared Seth Dept. of Computer Science Washington University St. Louis MO Dept. of Computer Science and Engineering University of Nebraska-Lincoln Lincoln NE

ISBN: (纸本)9780897917438

A genetic algorithm (GA) is a robust problem-solving method based on natural selection. Hardware's speed advantage and its ability to parallelize offer great rewards to genetic algorithms. Speedups of 1-3 orders of magnitude have been observed when frequently used software routines were implemented in hardware by way of reprogrammable field-programmable gate arrays (FPGAs). Reprogrammability is essential in a general-purpose GA engine because certain GA modules require changeability (e.g. the function to be optimized by the GA). Thus a hardware-based GA is both feasible and desirable. A fully functional hardware-based genetic algorithm (the HGA) is presented here as a proof-of-concept system. It was designed using VHDL to allow for easy scalability. It is designed to act as a coprocessor with the CPU of a PC. The user programs the FPGAs which implement the function to be optimized. Other GA parameters may also be specified by the user. Simulation results and performance analyses of the HGA are presented. A prototype HGA is described and compared to a similar GA implemented in software. In the simple tests, the prototype took about 6% as many clock cycles to run as the software-based GA. Further suggested improvements could realistically make the HGA 2–3 orders of magnitude faster than the software-based GA.

关键词： function optimization performance evaluation performance acceleration parallel genetic algorithms field programmable gate arrays

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HMLib: Efficient Data Transfer for HLS Using Host Memory 23

HMLib: Efficient Data Transfer for HLS Using Host Memory

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proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Michael Lo Young-kyu Choi Weikang Qiao Mau-Chung Frank Chang Jason Cong University of California Los Angeles Los Angeles CA USA Inha University Incheon Republic of Korea

ISBN: (纸本)9781450394178

Streaming applications compose an important portion of the workloads that FPGAs may accelerate but suffer from inefficient data movement. The inefficiency stems from copying data indirectly into the FPGA DRAM rather than directly into its on-chip memory, substantially diminishing the end-to-end speedup, especially for small workloads (hundreds of kilobytes). AMD Xilinx's Host Memory IP (HMI) aims to address the data movement problem by exposing to the developer an High-Level Synthesis (HLS) interface that moves the data from the host directly to the FPGA's on-chip memory. However, using HMI purely for its interface without additional code changes incurred a 3.3x slowdown in comparison with the current programming model. The slowdown mainly originates from OpenCL call overhead and the kernel control logic unnecessarily switching states. To overcome these issues, we propose Host Memory Library (HMLib), an efficient HLS-based library that facilitates data transfer on behalf of the user. HMLib not only optimizes the runtime stack for efficient data transfer, but also provides HLS compatible and user-friendly interfaces. We demonstrate HMLib's effectiveness for streaming applications (Deflate compression and CRC32) with improvements of up to up to 36.2X over OpenCL-DDR and up to 79.5X over raw HMI for small-scale data while maintaining little-to-no performance loss for large scale inputs. We plan to open source our work in the future.

关键词： high-level synthesis field-programmable gate array on-chip memory host memory opencl streaming workload

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The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop 11

The role of FPGAs in a converged future with heterogeneous p...

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Jonathan Rose Guy Lemieux University of Toronto Toronto ON Canada University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781450305549

The battle of fixed function devices vs. programmable devices has been won by the programmables. The question facing us now is to determine what kinds of programmability to place on next generation systems/devices. Research and development on many applications has shown that different kinds of hardware and software programmability succeed for different application classes: powerful, singlethread-optimized CPUs continue to do very well for many applications; the General Purpose GPU is carving a niche in high throughput, parallel floating point codes in addition to its home turf of graphics; the FPGA is particularly good at variable bit-size computations and data steering, as well as parallel distributed control of networks. Future systems may well need all three types of these types of engines, and perhaps interesting mixtures of them. This is particularly true when we deal with the combined goals of optimizing cost, performance and *** this workshop, we will look to the future of the FPGA within these types of 'converged' programmable computing engines, and reflectively ask ourselves: What role can the FPGA play? What future applications in areas such as networking, mobile, and artificial intelligence can be driven by FPGAs? How do FPGAs fit into the architecture realm of CPUs, general purpose GPUs, and DSPs? How should the designer/programme express their intent in the most effective way possible? What are the requirements for a compilation and optimization environment that allow FPGAs to intermix within a heterogeneous and converged future?The intent of this workshop is to open a discussion on these questions. There will be a series of short, invited talks interspersed with free and open discussion.

关键词： heterogeneity reconfigurable computing high level programming models fpga heterogeneous computing systems signal processing dsp

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A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory arrays (Abstract Only) 15

A Hardware Implementation of a Unit for Geometric Algebra Op...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Gerardo Soria García Adrian Pedroza de la Cruz Susana Ortega Cisneros Juan José Raygoza Panduro Eduardo Bayro Corrochano Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional Zapopan Mexico Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional zapopan Mexico Universidad de Guadalajara Guadalajara Mexico

ISBN: (纸本)9781450333153

Geometric algebra (GA) is a powerful and versatile mathematical tool which helps to intuitively express and manipulate complex geometric relationships. It has recently been used in engineering problems such computer graphics, machine vision, robotics, among others. The problem with GA in its numeric version is that it requires many arithmetic operations, and the length of the input vectors is unknown until runtime in a generic architecture operating over homogeneous elements. Few works in hardware architectures for GA were developed to improve the performance in GA applications. In this work, a hardware architecture of a unit for GA operations (geometric product) for FPGA is presented. The main contribution of this work is the use of parallel memory arrays with access conflict avoidance for dealing with the issue of unknown length of input/output vectors, the intention is to reduce memory wasted when storing the input and output vectors. In this first stage of the project, we have implemented only a single access function (fixed-length) in the memory array in order to test the core of geometric product. In future works we will implement a full set of access functions with different lengths and shapes. In this work, only the simulations are presented; in the future, we will also present the experimental results

关键词： fpga address generator geometric product. geometric algebra memory arrays

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Computation-in-memory based parallel adder

Computation-in-memory based parallel adder

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IEEE international symposium on Nanoscale Architectures (NANOARCH)

作者： Hoang Anh Du Nguyen Lei Xie Mottaqiallah Taouil Razvan Nane Said Hamdioui Koen Bertels Laboratory of Computer Engineering Faculty of EE Mathematics and CS Delft University of Technology Delft Zuid-Holland NL Laboratory of Computer Engineering Faculty of EE Mathematics and CS Delft University of Technology Delft CD The Netherlands

Today's computing systems suffer from memory/communication bottleneck, resulting in energy and performance inefficiency. This makes them incapable to solve data-intensive applications within economically acceptable limits. Computation-In-Memory (CIM) architecture, based on the integration of storage and computation in the same physical location using non-volatile memristor technology offers a potential solution for the memory bottleneck. This paper presents a CIM based parallel adder, and shows its potentials and superiority for intensive computing and massive parallelism by comparing it with state-of-the art computing systems including multicore, GPU and FPGA architecture. The results show that CIM based parallel adder can achieve at least two orders of magnitude improvement in computational efficiency, energy efficiency and area efficiency.

关键词： Adders Computer integrated manufacturing Graphics processing units Multicore processing field programmable gate arrays Delays

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FPGA Based Transmitter Design Using Adaptive Coding and Modulation Schemes for Low Earth Orbit Satellite Communications

FPGA Based Transmitter Design Using Adaptive Coding and Modu...

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IEEE international symposium on Telecommunication Technologies (ISTT)

作者： Erkan İnceöz Raşit Tutgun Ayşe Melda Yüksel Turgut TOBB University of Economics and Technology Ankara Turkey The Scientific and Technological Research Council of Turkey Ankara Turkey

ISBN: (数字)9781728181615

ISBN: (纸本)9781728181622

In this study, a field-programmable gate array (FPGA) based high rate transmitter is developed for low earth orbit satellite communication links using adaptive coding and modulation (acm) techniques. The developed transmitter structure is modeled in MATLAB. Then, the MATLAB model is taken as reference for developing an FPGA design. This design is implemented on Xilinx Kintex Ultrascale XCKU060 FPGA which provides high performance and whose space grade model will be on product line in December 2020. It is shown that the developed transmitter structure can reach a spectral efficiency of 7.068 bits per second per Hertz (bps/Hz) with a code rate of 0.8889 in the highest rate mode. The implemented FPGA design of the transmitter structure can support input data rates from 50.7225 megabits per second (Mbps) to 530.1 Mbps with a baud rate of 75 mega symbol per second (Msps) and a sampling rate of 300 mega sample per second (MSps) at the output.

关键词： Transmitters field programmable gate arrays Modulation Convolutional codes Satellites Low earth orbit satellites Signal to noise ratio

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Modeling a reconfigurable system for computing the FFT in place via rewriting-logic 03

Modeling a reconfigurable system for computing the FFT in pl...

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symposium on Integrated Circuits and Systems Design (SBCCI)

作者： M. Ayala-Rincon R.B. Nogueira C.H. Llanos R.P. Jacobi R.W. Hartenstein Departamentos de Matemática Universidade de Brasília Brazil Engenharia Mecânica Universidade de Brasília Brazil Ciência da Computação Universidade de Brasília Brazil Fachbereich Informatik Universität Kaiserslautern Germany

ISBN: (纸本)9780769520094

The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectures, the choice of an efficient architecture and reconfiguration scheme for a given application is a complex task. Tools for exploration of design alternatives at higher abstraction levels are needed. This paper describes the modeling and simulation of a dynamically reconfigurable hardware implementation of the fast Fourier transform (FFT) using rewriting-logic. It is shown that rewriting-logic can be used as a framework for fast design space exploration, providing a quick evaluation of different reconfigurable solutions.

关键词： Hardware field programmable gate arrays Brazil Council Reconfigurable architectures Computational modeling Signal processing algorithms Application specific integrated circuits Costs Computer architecture Circuit simulation

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Efficient FPGA Implementation of Conjugate Gradient Methods for Laplacian System using HLS 19

Efficient FPGA Implementation of Conjugate Gradient Methods ...

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proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Sahithi Rampalli Natasha Sehgal Ishita Bindlish Tanya Tyagi Pawan Kumar International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781450361378

In conjugate gradient method to solve partial differential equations, matrix vector operations are required in each iteration; these matrix vector operations can be implemented as 5 point finite difference stencil operations on the grid without explicitely constructing the matrix. We show that a pipelined and superscalar design using high level synthesis (HLS) leads to a significant reduction in latencies for two variants of conjugate gradient methods considered. When comparing these two, we show that the second method has roughly two times lower latency than the former given the same degree of superscalarity. These reductions in latencies for the newer variant of CG is due to parallel implementations of stencil operation on subdomains of the grid, and due to overlap of these stencil operations with dot product operations. In a superscalar design for the stencil operation, the computational domain needs to be partitioned, and boundary data needs to be copied, which requires padding. We propose a novel traversal of the grid for 2D domain decomposition that leads to reduction in latency cost involved with padding. The FPGA implementation of CG is roughly 7 times faster than state-of- the-art sequential implementation, and roughly 4 times faster than state-of-the-art CUDA library parallel implementation for the linear system of dimension 10000 x 10000.

关键词： fpga high level synthesis laplace system pipelining superscalarity conjugate gradient

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Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only) 16

Re-targeting Optimization Sequences from Scalar Processors t...

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proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Ronak Kogta Suresh Purini Ajit Mathew International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781450338561

A high-level synthesis compiler translates a source program written in a high level programming language such as C or SystemC into an equivalent circuit. The performance of the generated circuit in terms of metrics such as area, frequency and clock cycles depends on the compiler optimizations enabled and their order of application. Finding an optimal sequence for a given program is a hard combinatorial optimization problem. In this paper, we propose a practical and search time efficient technique for finding a near-optimal sequence for a given program. The main idea is to strike a balance between the search for a universally good sequence (like that of O3) which works for all programs vis-a-vis finding a good sequence on a per-program basis. Towards that, we construct a rich downsampled sequence set, which caters to different program classes, from the unbounded optimization sequence space by applying heuristic search algorithms on a set of Microkernel benchmark programs. The optimization metric that we use while constructing the downsampled sequence set is the execution time on a scalar processor. Given a new program, we try all the sequences from the downsampled sequence setand pick the best. Applying this technique in the LegUp high-level synthesis compiler, we are able to obtain 23% and 40% improvement on CHStone and Machsuite benchmark programs respectively. We also propose techniques to further reduce the size of the downsampled sequence set to improve the sequence search time.

关键词： high level synthesis optimization compilers

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