The proceedings contain 23 papers. The topics discuss include: CompressedLUT: an open-source tool for lossless compression of lookup tables for function evaluation and beyond;MiCache: an MSHR-inclusive non-blocking ca...
ISBN:
(纸本)9798400704185
The proceedings contain 23 papers. The topics discuss include: CompressedLUT: an open-source tool for lossless compression of lookup tables for function evaluation and beyond;MiCache: an MSHR-inclusive non-blocking cache design for FPGAs;Hardcaml MSM: a high-performance split CPU-FPGA multi-scalar multiplication engine;DynaRapid: from C to FPGA in a few seconds;design and implementation of a primary visual cortex pathway model based on opponent-process theory;Hardcaml: an OCaml hardware domain-specific language for efficient and robust design;XUNI: virtual machine abstraction for self-contained and multi-tenant cloud FPGAs;ISO-TENANT: rethinking FPGA power distribution network (PDN): a hardware based solution for remote power side channel attacks in FPGA;and accelerating autonomous path planning on FPGAs with sparsity-aware HW/SW co-optimizations.
The proceedings contain 25 papers. The topics discussed include: FlightVGM: efficient video generation model inference with online sparsification and hybrid precision on FPGAs;TreeLUT: an efficient alternative to deep...
ISBN:
(纸本)9798400713965
The proceedings contain 25 papers. The topics discussed include: FlightVGM: efficient video generation model inference with online sparsification and hybrid precision on FPGAs;TreeLUT: an efficient alternative to deep neural networks for inference acceleration using gradient boosted decision trees;greater than the sum of its LUTs: scaling up LUT-based neural networks with AmigoLUT;wa-hls4ml and lui-gnn: a benchmark and GNN based surrogate model for hls4ml resource and latency estimation;InTRRA: inter-task resource-repurposing accelerator for efficient transformer inference on FPGAs;DPUV4E: high-throughput DPU architecture design for CNN on versal ACAP;and performance analysis of GEMM workloads on the AMD versal platform.
The proceedings contains 24 papers from the acm/sigdainternationalsymposium on fieldprogrammablegatearrays - FPGA 2004. The topics discussed include: exploration of pipelined FPGA interconnect structures;evaluati...
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The proceedings contains 24 papers from the acm/sigdainternationalsymposium on fieldprogrammablegatearrays - FPGA 2004. The topics discussed include: exploration of pipelined FPGA interconnect structures;evaluation of low leakage design techniques for fieldprogrammablegatearrays;reducing leakage energy in FPGAs using region constrained placement;an embedded true random number generator for FPGAs;a synthesis oriented omniscient manual editor;nanowire-based sublithographic programmable logic arrays;and highly pipelined asynchronous FPGAs.
The proceedings contains 25 papers from the 1998 acm/sigdainternationalsymposium on fieldprogrammablegatearrays (FPGA). Topics discussed include: new FPGA architectures;technology mapping for FPGAs;multi-FPGA sys...
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The proceedings contains 25 papers from the 1998 acm/sigdainternationalsymposium on fieldprogrammablegatearrays (FPGA). Topics discussed include: new FPGA architectures;technology mapping for FPGAs;multi-FPGA systems & other reprogrammable architectures;partitioning and floor planning for FPGAs;fault detection and fault tolerance for FPGAs;fast computer aided design (CAD) tools for FPGAs;time multiplexed FPGAs;FPGAs with embedded memory;and programmable architectures with special features.
The proceedings contain 64 papers from the acm/sigda Thirteenth acminternationalsymposium on fieldprogrammablegatearrays - FPGA 2005. The topics discussed include: the Stratix II logic and routing architecture;sk...
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The proceedings contain 64 papers from the acm/sigda Thirteenth acminternationalsymposium on fieldprogrammablegatearrays - FPGA 2005. The topics discussed include: the Stratix II logic and routing architecture;skew-programmable clock design for FPGA and skew-aware placement;sparse matrix-vector multiplication on FPGAs;power modeling and architecture evaluation for FPGA with novel circuits for VDD programmability;architecture adaptive routability-driven placement for FPGAs;energy-efficient FPGA interconnect architecture design;3D-Softchip: A novel 3D vertically integrated adaptive computing system;dynamic reconfiguration in FPGA-based SoC designs;and rapid prototyping of a test harness for forward error correcting codes.
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