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检索条件"任意字段=Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 795 条记录，以下是91-100 订阅

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Optimizations for a highly cost-efficient programmable logic architecture 98

Optimizations for a highly cost-efficient programmable logic...

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Veenstra, Kerry Pedersen, Bruce Schleicher, Jay Sung, Chiakang Altera Corp San Jose CA United States

ISBN: (纸本)9780897919784

Architects of programmable logic devices (PLDs) face several challenges when optimizing a new device family for low manufacturing cost. When given an aggressive die-size goal, functional blocks that seem otherwise insignificant become targets for area reduction. Once low die cost is achieved, it is seen that testing and packaging costs must be considered. Interactions among these three cost contributors pose trade-offs that prevent independent optimization. This paper discusses solutions discovered by the architects optimizing the Altera FLEX 6000 architecture.

关键词： programmable logic controllers

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Network-on-Chip programmable Platform in Versal™ ACAP Architecture

Network-on-Chip Programmable Platform in Versal™ ACAP Archi...

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Swarbrick, Ian Gaitonde, Dinesh Ahmad, Sagheer Gaide, Brian Arbel, Ygal Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781450361378

This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal (TM) architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture devices. These devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) devices. There is a trend in FPGA devices of hardening many commonly used components such as processors, memory controllers and other IO controllers. The next generation of Xilinx devices take this a step further by providing a device-global memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, FPGA fabric, memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.

关键词： ACAP Versal FPGA Stacked Silicon SSIT Adaptable Compute Acceleration Platform NoC FPGA Architecture FPGA CAD Xilinx

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High-Performance QR Decomposition for FPGAs 18

High-Performance QR Decomposition for FPGAs

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acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Langhammer, Martin Pasca, Bogdan Intel Programmable Solut Grp Swindon Wilts England Intel Programmable Solut Grp Paris France

ISBN: (纸本)9781450356145

QR decomposition (QRD) is of increasing importance for many current applications, such as wireless and radar. Data dependencies in known algorithms and approaches, combined with the data access patterns used in many of these methods, restrict the achievable performance in software programmable targets. Some FPGA architectures now incorporate hard floating-point (HFP) resources, and in combination with distributed memories, as well as the flexibility of internal connectivity, can support high-performance matrix arithmetic. In this work, we present the mapping to parallel structures with inter-vector connectivity of a new QRD algorithm. Based on a Modified Gram-Schmidt (MGS) algorithm, this new algorithm has a different loop organization, but the dependent functional sequences are unchanged, so error analysis and numerical stability are unaffected. This work has a theoretical sustained-to-peak performance close to 100% for large matrices, which is roughly three times the functional density of the previously best known implementations. Mapped to an Intel Arria 10 device, we achieve 80us for a 256x256 single precision real matrix, for a 417 GFLOP equivalent. This corresponds to a 95% sustained to peak ratio, for the portion of the device used for this work.

关键词： QRD MGS FPGA Arria10 throughput

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Quantifying the cost and benefit of latency insensitive communication on FPGAs 14

Quantifying the cost and benefit of latency insensitive comm...

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Murray, Kevin E. Betz, Vaughn Dept. of Electrical and Computer Engineering University of Toronto Ontario Canada

ISBN: (纸本)9781450326711

Latency insensitive communication oers many potential benets for FPGA designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to understand the costs and trade-os associated with any new design style. This paper presents optimized implementations of latency insensitive communication building blocks, quanties their overheads in terms of area and frequency, and provides guidance to designers on how to generate high-speed and areae cient latency insensitive systems.

关键词： field programmable gate arrays (FPGA)

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FPGA Acceleration for Computational Glass-Free Displays 17

FPGA Acceleration for Computational Glass-Free Displays

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acm/sigda international symposium on field-programmable gate arrays

作者： He, Zhuolun Luo, Guojie Peking Univ Sch EECS Ctr Energy Efficient Comp & Applicat Beijing Peoples R China NUDT Collaborat Innovat Ctr High Performance Comp Changsha Hunan Peoples R China PKU UCLA Joint Res Inst Sci & Engn Beijing Peoples R China

ISBN: (纸本)9781450343541

The increasing computational power enables various new applications that are runtime prohibitive before. FPGA is one of such computational power with both reconfigurability and energy efficiency. In this paper, we demonstrate the feasibility of eyeglasses-free displays through FPGA acceleration. Specifically, we propose several techniques to accelerate the sparse matrix-vector multiplication and the L-BFGS iterative optimization algorithm with the consideration of the characteristics of FPGAs. The experimental results show that we reach a 12.78X overall speedup of the glass-free display application.

关键词： fpga accelerator l-bfgs algorithm sparse matrix-vector multiplication light field display

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Location, location, location - The role of spatial locality in asymptotic energy minimization 13

Location, location, location - The role of spatial locality ...

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2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： DeHon, André M. Department of Electrical and Systems Engineering University of Pennsylvania 200 S. 33rd St. Philadelphia PA 19104 United States

ISBN: (纸本)9781450318877

Locality exploitation is essential to asymptotic energy minimization for gate array netlist evaluation. Naive implementations that ignore locality, including flat crossbars and simple processors based on monolithic memories, can require O(N2) energy for an N node graph. Specifically, it is important to exploit locality (1) to reduce the size of the description of the graph, (2) to reduce data movement, and (3) to reduce instruction movement. FPGAs exploit all three. FPGAs with a Rent Exponent p © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Managing pipeline-reconfigurable FPGAs 98

Managing pipeline-reconfigurable FPGAs

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Cadambi, Srihari Weener, Jeffrey Goldstein, Seth Copen Schmit, Herman Thomas, Donald E. Carnegie Mellon Univ Pittsburgh PA United States

ISBN: (纸本)9780897919784

While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using a combination of pipeline reconfiguration and run-time scheduling of both configuration streams and data streams. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis predicts that PipeRench will outperform commercial FPGAs and DSPs in both overall performance and in performance per mm2.

关键词： field programmable gate arrays

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Partitioning sequential circuits on dynamically reconfigurable FPGAs

Partitioning sequential circuits on dynamically reconfigurab...

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proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Chang, Douglas Marek-Sadowska, Malgorzata Univ of California Santa Barbara Santa Barbara United States

A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and interconnect is time-multiplexed. Thus for a circuit to be implemented on a DRFPGA, it needs to be partitioned such that each subcircuit can be executed at a different time. In this paper, the partitioning of sequential circuits for execution on a DRFPGA is studied. To determine how to correctly partition a sequential circuit, and what are the costs in doing so, we propose a new gate-level model that handles time-multiplexed computation. We also introduce an enhanced force directed scheduling (FDS) algorithm to partition sequential circuits that finds a correct partition with low logic and communication costs, under the assumption that maximum performance is desired. We use our algorithm to partition seven large ISC AS'89 sequential benchmark circuits. The experimental results show that the enhanced FDS reduces communication costs by 27.5% with only a 1.1% increase in the gate cost compared to traditional FDS.

关键词： field programmable gate arrays

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A high performance FPGA-based implementation position specific iterated BLAST

A high performance FPGA-based implementation position specif...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Kasap, Server Benkrid, Khaled Liu, Ying University of Edinburgh United Kingdom School of Electronics and Engineering Mayfield Road Edinburgh EH9 3JL United Kingdom

ISBN: (纸本)9781605584102

We present in this paper the first reported FPGA implementation of the Position Specific Iterated BLAST (PSI-BLAST) algorithm. The latter is a heuristic biological sequence alignment algorithm that is widely used in the bioinformatics and computational biology world in order to detect weak homologs. The architecture of our FPGA implementation is parameterized in terms of sequence lengths, scoring matrix, gap penalties and cut-off and threshold values. It is composed of various blmocks each of which performs one step of the algorithm in parallel. This results in high performance implementations, which easily outperform equivalent software implementations by one order of magnitude or more. Furthermore, the core was captured in an FPGA-platformindependent language, namely the Handel-C language, to which no specific resource inference or placement constraints were applied. This makes our core portable across different FPGA families and architectures. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Magnetic tunnelling junction based FPGA 06

Magnetic tunnelling junction based FPGA

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Bruchon, Nicolas Torres, Lionel Sassatelli, Gilles Cambon, Gaston LIRMM 161 rue Ada 34392 Montpellier Cedex 5 France

ISBN: (纸本)1595932925

The aim of this paper is to propose a real time reconfigurable (RTR) micro-FPGA using new non volatile memory. Magnetic tunneling junctions (MTJ) used in Magnetic random access memories (MRAM.) are compatible with classical CMOS processes. Moreover remanent property of such a memory could limit configuration time and power consumption required at each power up of the die. Nevertheless, each configuration memory point has to be readable independently from each other, that is why the approach is different from the classical memory array one. Copyright 2006 acm.

关键词： field programmable gate arrays

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