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检索条件"任意字段=Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 795 条记录，以下是121-130 订阅

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Embedded floating-point units in FPGAs 06

Embedded floating-point units in FPGAs

引用

14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Beauchamp, Michael J. Hauck, Scott Underwood, Keith D. Hemmert, K. Scott University of Washington Dept. of Electrical Engineering United States Sandia National Laboratories Scalable Computing Systems United States

ISBN: (纸本)1595932925

Due to their generic and highly programmable nature, FPGAs provide the ability to implement a wide range of applications. However, it is this nonspecific nature that has limited the use of FPGAs in scientific applications that require floating-point arithmetic. Even simple floating-point operations consume a large amount of computational resources. In this paper, we introduce embedding floating-point multiply-add units in an island style FPGA. This has shown to have an average area savings of 55.0% and an average increase of 40.7% in clock rate over existing architectures. Copyright 2006 acm.

关键词： field programmable gate arrays

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RapidSmith 2: A framework for BEL-level CAD exploration on Xilinx FPGAs 15

RapidSmith 2: A framework for BEL-level CAD exploration on X...

引用

acm/sigda international symposium on field-programmable gate arrays, FPGA 2015

作者： Haroldsen, Travis Nelson, Brent Hutchings, Brad Department of Electrical and Computer Engineering Brigham Young University ProvoUT84602 United States

ISBN: (纸本)9781450333153

RapidSmith is an open-source framework that allows for the exploration of novel approaches to the FPGA CAD flow for Xilinx devices. However, RapidSmith has poor sup- port for manipulating designs below the slice level. In this paper, we highlight many of the projects RapidSmith en- ables and present extensions incorporated into "RapidSmith 2" that expose LUTs and ip-ops for direct manipulation in custom-built CAD tools. To demonstrate the utility of RapidSmith 2 we present the results of work to identify BELs in a design which must be clustered together and a tool that does pre-packing clustering accordingly. © Copyright acm.

关键词： field programmable gate arrays (FPGA)

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A remote memory access infrastructure for global address space programming models in FPGAs 13

A remote memory access infrastructure for global address spa...

引用

2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Willenberg, Ruediger Chow, Paul Dept. of Electrical and Computer Engineering University of Toronto Toronto ON Canada

ISBN: (纸本)9781450318877

We are proposing a shared-memory communication infrastructure that provides a common parallel programming interface for FPGA and CPU components in a heterogeneous system. Our intent is to ease the integration of reconfigurable hardware into parallel programming models like Partitioned Global Address Space (PGAS). For this purpose, we introduce a remote memory access component based on Active Messages that implements the core API of the Berkeley GASNet communication library, and a simple controller that manages communication and synchronization for custom FPGA cores. We demonstrate how these components deliver a simple and easily configurable communication mechanism between distributed memories in a multi-FPGA system with processors as well as custom hardware nodes. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Dynamic reconfiguration in FPGA-based SoC designs

Dynamic reconfiguration in FPGA-based SoC designs

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Bartosinski, Roman Daněk, Martin Honzik, Petr Matoušek, Rudolf Inst. of Information Theory and Automatioru Czech Academy of Sciences Pod vodarenskou vezi 4 182 08 Praha 8 Czech Republic

This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip designs with microprocessors with fixed instruction sets. Further a sample application is discussed that uses a dynamically reconfigurable FPGA to implement different floating-point calculations in hardware, reconfigured as required by the execution of the user code. The implementation data for two dynamically reconfigurable platforms available on the market - the Xilinx Virtex2 family FPGAs and the Atmel FPSLIC family FPGAs - is compared in terms of resource requirements, operating frequency, and power consumption.

关键词： field programmable gate arrays

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Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs 05

Analysis of yield loss due to random photolithographic defec...

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Campregher, Nicola Cheung, Peter Y. K. Vasilko, Milan Constantinides, George A. Electrical and Electronic Engineering Imperial College London United Kingdom School of Design Engineering and Computing Bournemouth University United Kingdom

ISBN: (纸本)9781595930293

This paper presents an analysis of the potential yield loss in FPGA due to random defects in metal layers. A proven yield model is adapted to target the FPGA interconnect layers in order to predict the manufacturing yield. Defect parameters from the 2003 SIA roadmap are used to investigate the trend in yield loss due to defects in interconnect layers in the future. It is shown that the low yield predicted for the 45nm technology node and beyond is a cause for concern. The potential impact on yield using two different approaches, namely redundant circuits and fault tolerant design, is also presented. Copyright 2005 acm.

关键词： field programmable gate arrays

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Automated synthesis for asynchronous FPGAs 05

Automated synthesis for asynchronous FPGAs

引用

acm/sigda Thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Peng, Song Fang, David Teifel, John Manohar, Rajit Computer Systems Laboratory Cornell University Ithaca NY 14853 United States Advanced Microelectronics Department Sandia National Laboratories United States

ISBN: (纸本)9781595930293

Advanced Microelectronics Department at Sandia National Laboratories. We present an automatic logic synthesis method targeted for high-performance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-level descriptions of asynchronous circuits into fine-grain asynchronous process netlists suitable for an AFPGA. The resulting circuits are inherently pipelined, and can be physically mapped onto our AFPGA with standard partitioning and place-and-route algorithms. For a wide variety of benchmarks, our automatic synthesis method not only yields comparable logic densities and performance to those achieved by hand placement, but also attains a throughput close to the peak performance of the FPGA. Copyright 2005 acm.

关键词： field programmable gate arrays

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Post-placement C-slow retiming for the xilinx virtex FPGA

Post-placement C-slow retiming for the xilinx virtex FPGA

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Weaver, Nicholas Markovskiy, Yury Patel, Yatish Wawrzynek, John UC Berkeley Berkeley CA United States

C-slow retiming is a process of automatically increasing the throughput of a design by enabling fine grained pipelining of problems with feedback loops. This transformation is especially appropriate when applied to FPGA designs because of the large number of available registers. To demonstrate and evaluate the benefits of C-slow retiming, we constructed an automatic tool which modifies designs targeting the Xilinx Virtex family of FPGAs. Applying our tool to three benchmarks: AES encryption. Smith/Waterman sequence matching, and the LEON 1 synthesized microprocessor core, we were able to substantially increase the total throughput. For some parameters, throughput is effectively doubled.

关键词： field programmable gate arrays

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Efficiently supporting fault-tolerance in FPGAs 98

Efficiently supporting fault-tolerance in FPGAs

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Lach, John Mangione-Smith, William H. Potkonjak, Miodrag UCLA EE Dep Los Angeles CA United States

ISBN: (纸本)9780897919784

While system reliability is conventionally achieved through component replication, we have developed a fault-tolerance approach for FPGA-based systems that comes at a reduced cost in terms of design time, volume, and weight. We partition the physical design into a set of tiles. In response to a component failure, we capitalize on the unique reconfiguration capabilities of FPGAs and replace the affected tile with a functionally equivalent tile that does not rely on the faulty component. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors, this approach allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead.

关键词： field programmable gate arrays

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An iterative division algorithm for FPGAs 06

An iterative division algorithm for FPGAs

引用

14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Liu, Jianhua Chang, Michael Cheng, Chung-Kuan Computer Science and Engineering Department University of California San Diego 92093 United States

ISBN: (纸本)1595932925

Division is one of the most complicated and expensive arithmetic operations. Both clock frequency and operation delay are limited by the memory wall, even in LUT-based FPGA devices. To conquer the memory limitation, we propose a hybrid division algorithm which employs Prescaling, Series expansion and Taylor expansion (PST) algorithms. The proposed algorithm boosts very-high radix division efficiently. The algorithm is multiplicative, and feasible for the modern FPGA devices with build-in multipliers. The algorithm is implemented in Altera StratixII FPGA devices and compared with the division IP core generated by Mega Wizard. The result shows that the PST algorithm has higher clock frequency, lower execution time and also lower power consumption. Copyright 2006 acm.

关键词： field programmable gate arrays

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field programmable Port Extender (FPX) for distributed routing and queuing 00

Field Programmable Port Extender (FPX) for distributed routi...

引用

FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Lockwood, John W. Turner, Jon S. Taylor, David E. Washington Univ Saint Louis MO United States

ISBN: (纸本)9781581131932

field programmable gate arrays (FPGAs) are being used to provide fast Internet Protocol (IP) packet routing and advanced queuing in a highly scalable network switch. A new module, called the field-programmable Port Extender (FPX), is being built to augment the Washington University Gigabit Switch (WUGS) with reprogrammable logic. FPX modules reside at the edge of the WUGS switching fabric. Physically, the module is inserted between an optical line card and the WUGS gigabit switch back-plane. The hardware used for this project allows ports of the switch populated with an FPX to operate at rates up to 2.4 Gigabits/second. The aggregate throughput of the system scales with the number of switch ports. Logic on the FPX module is implemented with two FPGA devices. The first device is used to interface between the switch and the line card, while the second is used to prototype new networking functions and protocols. The logic on the second FPGA can be re-programmed dynamically via control cells sent over the network.

关键词： field programmable gate arrays

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