The Third international Workshop on Overlay Architectures for FPGAs (OLAF) is held in Monterey, California, USA, on Feburary 22, 2017 and co-located with FPGA 2017: The 25th acm/sigdainternationalsymposium on field ...
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ISBN:
(纸本)9781450343541
The Third international Workshop on Overlay Architectures for FPGAs (OLAF) is held in Monterey, California, USA, on Feburary 22, 2017 and co-located with FPGA 2017: The 25th acm/sigdainternationalsymposium on fieldprogrammablegatearrays. The main objective of the workshop is to address how overlay architectures can help address the challenges and opportunites provided by FPGA-based reconfigurable computing. The workshop provides a venue for researchers to present and discuss the latest developments in FPGA overlay architecture and related areas. We have assembled a program of six refereed papers with panel discussions with prominent experts in the field.
The Second international Workshop on Overlay Architectures for FPGAs is held in Monterey, California, USA, on February 21, 2016 and co-located with FPGA 2016: The 24th acm/sigdainternationalsymposium on field Progra...
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ISBN:
(纸本)9781450338561
The Second international Workshop on Overlay Architectures for FPGAs is held in Monterey, California, USA, on February 21, 2016 and co-located with FPGA 2016: The 24th acm/sigdainternationalsymposium on fieldprogrammablegatearrays. The main objective of the workshop is to address how overlay architectures can help address the challenges and opportunities provided by FPGA-based reconfigurable computing. The workshop provides a venue for researchers to present and discuss the latest developments in FPGA overlay architecture and related areas. We have assembled a program of six refereed papers and a panel discussion with prominent experts in the field.
In this paper we propose new techniques for thermal and power characterization of fieldprogrammablegatearrays (FPGAs) using infrared imaging techniques. For thermal characterization, we capture the thermal emission...
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ISBN:
(纸本)9781450305549
In this paper we propose new techniques for thermal and power characterization of fieldprogrammablegatearrays (FPGAs) using infrared imaging techniques. For thermal characterization, we capture the thermal emissions from the backside of an FPGA chip during operation. We analyze the captured emissions and quantify the extent of thermal gradients and hot spots in FPGAs. Given that FPGAs are fabricated with no knowledge of the potential field designs, we propose soft sensing techniques that can combine the measurements of hard sensors to accurately estimate the temperatures where no sensors are embedded. For power characterization, we propose algorithmic techniques to invert the thermal emissions from FPGAs into spatial power estimates. We demonstrate how this technique can be used to produce spatial power maps of soft processors during operation.
This paper describes the architectural configuration of the Electrically programmable Analog Circuit (EPAC), an expert cell approach to meeting the market need for an analog counterpart to the digital FPGA. It provide...
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This paper describes the architectural configuration of the Electrically programmable Analog Circuit (EPAC), an expert cell approach to meeting the market need for an analog counterpart to the digital FPGA. It provides an overview of the technology and describes the internal operation of the first commercial EPAC devices.
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavo...
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ISBN:
(纸本)9781605584102
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex protocol. The implementation is described and its performance is analyzed. Source code is offered for free download via the web. Copyright 2009 acm.
The proceedings contains 26 papers from the FPGA 2002 Tenth acminternationalsymposium on field-programmablegatearrays. Topics discussed include: interconnect enhancements for a high-speed PLD architecture;FPGA swi...
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The proceedings contains 26 papers from the FPGA 2002 Tenth acminternationalsymposium on field-programmablegatearrays. Topics discussed include: interconnect enhancements for a high-speed PLD architecture;FPGA switch block layout and evaluation;a faster distributed arithmetic architecture for FPGAs;efficient circuit clustering for area and power reduction in FPGAs and integrated retiming and placement for fieldprogrammablegatearrays.
This article presents the performance evaluation of two new diagonal routing tracks in FPGAs. We discuss the automatic detailed architecture generation issues and propose changes in the conventional placement and rout...
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ISBN:
(纸本)9781605584102
This article presents the performance evaluation of two new diagonal routing tracks in FPGAs. We discuss the automatic detailed architecture generation issues and propose changes in the conventional placement and routing to suit these architectures better. We conduct a series of experiments on these architecture with MCNC Benchmarks, where key parameters are varied over practical ranges and we conclude that the results are well in accordance, as predicted by the theory. Copyright 2009 acm.
Multi-fieldprogrammablegate array (FPGA) systems (MFS) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture;...
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Multi-fieldprogrammablegate array (FPGA) systems (MFS) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture;the manner in which wires, FPGAs and fieldprogrammable interconnect devices (FPID) are connected. A new routing architecture, called hybrid complete-graph and partial-crossbar (HCGP), which has superior speed and cost compared to a partial crossbar is proposed. The architecture uses both hard-wired and programmable connections between the FPGAs.
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