检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

765 篇 会议
30 篇 期刊文献

馆藏范围

795 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

631 篇 工学
- 583 篇 计算机科学与技术...
- 345 篇 软件工程
- 267 篇 电子科学与技术（可...
- 186 篇 电气工程
- 109 篇 信息与通信工程
- 42 篇 控制科学与工程
- 41 篇 动力工程及工程热...
- 29 篇 机械工程
- 20 篇 生物工程
- 13 篇 建筑学
- 12 篇 仪器科学与技术
- 11 篇 冶金工程
- 11 篇 土木工程
- 9 篇 材料科学与工程（可...
- 9 篇 化学工程与技术
- 9 篇 生物医学工程（可授...
- 4 篇 光学工程
- 4 篇 农业工程
235 篇 理学
- 192 篇 数学
- 39 篇 物理学
- 21 篇 生物学
- 20 篇 统计学（可授理学、...
- 11 篇 系统科学
- 7 篇 化学
66 篇 管理学
- 55 篇 管理科学与工程(可...
- 36 篇 工商管理
- 12 篇 图书情报与档案管...
18 篇 经济学
- 18 篇 应用经济学
16 篇 法学
- 14 篇 社会学
4 篇 教育学
- 4 篇 教育学
4 篇 农学

主题

357 篇 field programmab...
241 篇 field programmab...
37 篇 signal processin...
36 篇 clocks
34 篇 ofdm
34 篇 estimation
33 篇 modulation
33 篇 filtration
30 篇 fpga
22 篇 hardware
17 篇 routing
15 篇 computer archite...
14 篇 switches
13 篇 table lookup
11 篇 logic arrays
11 篇 prototypes
10 篇 systolic arrays
10 篇 costs
9 篇 field-programmab...
9 篇 field-programmab...

机构

6 篇 univ of toronto ...
6 篇 imperial college...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 xilinx
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 university of ca...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 department of co...
3 篇 school of comput...

作者

21 篇 cong jason
20 篇 rose jonathan
12 篇 betz vaughn
10 篇 hauck scott
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
8 篇 chen deming
8 篇 langhammer marti...
7 篇 constantinides g...
7 篇 chow paul
6 篇 anderson jason h...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
5 篇 jason cong
5 篇 so hayden kwok-h...
5 篇 dehon andre

语言

784 篇 英文
11 篇 其他

检索条件"任意字段=Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 795 条记录，以下是51-60 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A communication architecture for complex runtime systems and its implementation on spartan-3 FPGAs

A communication architecture for complex runtime systems and...

引用

7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Koch, Dirk Beckhoff, Christian Teich, Jürgen University of Erlangen-Nuremberg Am Weichselgarten 3 D91058 Erlangen Germany

ISBN: (纸本)9781605584102

In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by FPGA reconfiguration at runtime. Furthermore, we examine how this architecture can be implemented on low-cost Spartan-3 devices. It will be demonstrated that modules can be exchanged in a system without disturbing the communication architecture. The paper points out, that the capabilities of Spartan-3 FPGAs are sufficient to build complex reconfigurable systems. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A Fast Discrete Placement Algorithm for FPGAs 12

A Fast Discrete Placement Algorithm for FPGAs

引用

20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Wu, Qinghong McElvain, Kenneth S. Synopsys Inc Mountain View CA 94043 USA

ISBN: (纸本)9781450311557

Good FPGA placement is crucial to obtain the best Quality of Results (QoR) from FPGA hardware. Although many published global placement techniques place objects in a continuous ASIC-like environment, FPGAs are discrete in nature, and a continuous algorithm cannot always achieve superior QoR by itself. Therefore, discrete FPGA-specific detail placement algorithms are used to improve the global placement results. Unfortunately, most of these detail placement algorithms do not have a global view. This paper presents a discrete "middle" placer that fills the gap between the two placement steps. It works like simulated annealing, but leverages various acceleration techniques. It does not pay the runtime penalty typical of simulated annealing solutions. Experiments show that with this placer, final QoR is significantly better than with the global-detail placer approach.

关键词： Computer-aided design (CAD) individual cell temperature window masking dynamic window field-programmable gate array (FPGA) placement simulated annealing

来源：评论

学校读者我要写书评

暂无评论

New retiming-based technology mapping algorithm for LUT-based FPGAs

New retiming-based technology mapping algorithm for LUT-base...

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Pan, Peichen Lin, Chih-Chang Clarkson Univ Potsdam United States

In this paper, we present a new retiming-based technology mapping algorithm for look-up table-based field programmable gate arrays. The algorithm is based on a novel iterative procedure for computing all k-cuts of all nodes in a sequential circuit, in the presence of retiming. The algorithm completely avoids flow computation which is the bottleneck of previous algorithms. Due to the fact that k is very small in practice, the procedure for computing all k-cuts is very fast. Experimental results indicate the overall algorithm is very efficient in practice.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

GlitchLess: An Active Glitch Minimization Technique for FPGAs 07

GlitchLess: An Active Glitch Minimization Technique for FPGA...

引用

15th acm/sigda international symposium on field-programmable gate arrays

作者： Lamoureux, Julien Lemieux, Guy G. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781595936004

This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable delay elements within the logic blocks of an FPGA to programmably align the arrival times of early-arriving signals to the inputs of the lookup tables and to filter out glitches generated by earlier circuitry. On average, the proposed technique eliminates 91% of the glitching, which reduces overall FPGA power by 18%. The added circuitry increases overall area by 5% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires no modifications to the existing FPGA routing architecture or CAD flow.

关键词： field-programmable gate arrays Power Minimization

来源：评论

学校读者我要写书评

暂无评论

Towards PVT-Tolerant Glitch-Free Operation in FPGAs 16

Towards PVT-Tolerant Glitch-Free Operation in FPGAs

引用

acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Huda, Safeen Anderson, Jason Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781450338561

Glitches are unnecessary transitions on logic signals that needlessly consume dynamic power. Glitches arise from imbalances in the combinational path delays to a signal, which may cause the signal to toggle multiple times in a given clock cycle before settling to its final value. In this paper, we propose a low-cost circuit structure that is able to eliminate a majority of glitches. The structure, which is incorporated into the output buffers of FPGA logic elements, suppresses pulses on buffer outputs whose duration is shorter than a configurable time window (set at the time of FPGA configuration). Glitches are thereby eliminated "at the source" ensuring they do not propagate into the high-capacitance FPGA interconnect, saving power. An experimental study, using Altera commercial tools for power analysis, demonstrates that the proposed technique reduces 70% of glitches, at a cost of 1% reduction in speed performance.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Design of a Logic Element for Implementing an Asynchronous FPGA 07

Design of a Logic Element for Implementing an Asynchronous F...

引用

15th acm/sigda international symposium on field-programmable gate arrays

作者： Smith, Scott C. Univ Missouri Dept Elect & Comp Engn Rolla MO 65462 USA

ISBN: (纸本)9781595936004

A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and can utilize embedded registration for gates with three or fewer inputs. The developed LE is compared with a previous NCL LE, showing that the one developed herein yields a more area efficient NCL circuit implementation. The NCL FPGA logic element is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process.

关键词： Asynchronous logic design delay-insensitive circuits field programmable gate Array (FPGA) NULL Convention Logic (NCL) reconfigurable logic

来源：评论

学校读者我要写书评

暂无评论

Wirelength modeling for homogeneous and heterogeneous FPGA architectural development

Wirelength modeling for homogeneous and heterogeneous FPGA a...

引用

7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Smith, Alastair M. Das, Joydip Wilton, Steven J.E. Department of Electrical and Computer Engineering University of British Columbia Canada

ISBN: (纸本)9781605584102

This paper describes an analytical model that relates the architectural parameters of an FPGA to the average prerouting wirelength of an FPGA implementation. Both homogeneous and heterogeneous FPGAs are considered. For homogeneous FPGAs, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the expected wirelength. For heterogeneous FPGAs, the number and positioning of the embedded blocks, as well as the number of pins on each embedded block is considered. Two applications of the model to FPGA architectural design are also presented. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A Synthesizable Datapath-Oriented Embedded FPGA Fabric 07

A Synthesizable Datapath-Oriented Embedded FPGA Fabric

引用

15th acm/sigda international symposium on field-programmable gate arrays

作者： Wilton, Steve J. E. Ho, C. H. Leong, Philip H. W. Luk, Wayne Quinton, Brad Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781595936004

We present an architecture for a synthesizable datapath-oriented field programmable gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a System-on-Chip (SoC). Our architecture is optimized for bus-based operations that are common in signal processing and computation intensive applications. It employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. We also describe a proof-of-concept layout of our core. It is shown that the proposed architecture is significantly more area efficient than the best previously reported synthesizable programmable logic core.

关键词： field programmable gate Array Datapath Synthesis Integrated Circuit System-on-Chip Embedded Block

来源：评论

学校读者我要写书评

暂无评论

A 475 MHz Manycore FPGA Accelerator for RTL Simulation 24

A 475 MHz Manycore FPGA Accelerator for RTL Simulation

引用

32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Kashani, Sahand Emami, Mahyar Kamahori, Keisuke Pourghannad, Sepehr Raj, Ritik Larus, James R. Epfl Lausanne Switzerland University of Washington Seattle United States Georgia Tech Atlanta United States

ISBN: (纸本)9798400704185

This paper presents the implementation of Manticore: a manycore accelerator for parallel RTL simulation. Manticore packs up to 225 custom soft processors running at 475 MHz on a large FPGA. Implementing manycore accelerators on FPGAs is challenging as designers must reconcile the conflicting goals of maximizing the number of cores on the chip and clocking them at the highest possible frequency. Designers face two classes of constraints: (1) architectural constraints imposed by a large FPGA's multi-die structure, and (2) physical constraints imposed by the FPGA shell's size and placement. Physical design therefore plays a critical role in the implementation of manycore accelerators. We present physical design challenges faced during Manticore's implementation on the AMD Alveo U200 card - -a large FPGA with a poorly-placed, wide shell that challenges physical implementation. © 2024 Owner/Author.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

FPGA technology mapping with encoded libraries and staged priority cuts

FPGA technology mapping with encoded libraries and staged pr...

引用

7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Kennings, Andrew Vorwerk, Kristofer Kundu, Arun Pevzner, Val Fox, Andy Actel Corporation 2061 Stierlin Court Mountain View CA 94043 United States

ISBN: (纸本)9781605584102

Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. We consider enhancements to a traditional LUTbased mapping algorithm for an FPGA comprised of logic blocks which implement only a subset of functions of up to k variables- specifically, the logic block is a partial LUT, but it possesses more inputs than typical LUTs. Numerical results are presented to demonstrate the efficacy of our proposed techniques using real circuits mapped to a commercial FPGA architecture. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共80页 << < 2 3 4 5 6 7 8 9 10 11 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：