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检索条件"任意字段=Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 795 条记录，以下是711-720 订阅

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Jet Determination in Liquid Argon Calorimeters Using a Heavily Interconnected System of field programmable gate arrays 00

Jet Determination in Liquid Argon Calorimeters Using a Heavi...

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proceedings of the 13th symposium on Integrated circuits and systems design

作者： B. Dulny J. Fent W. Haberer C. Kiesling A. Osthoff

ISBN: (纸本)9780769508436

New fast and highly complex field programmable gate arrays (FPGAs) allow the design of sophisticated decision logic within the trigger latency time of particle detectors. As an example we show the jet determination of the Hera-Hl detector at DESY (Deutsches Elektronen Synchrotron) Hamburg. It has to calculate all existing localized energy depositions (jets) in the calorimeter and deliver the result, sorted according to energy. The system is implemented by a network of 3/spl times/440 high density FPGA's which have to deliver the results in less than 1 /spl mu/s. The computing power of the system is equivalent to 70 billion operations per second.

关键词： 1 mus

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An Automated Design Framework for Floating Point Scientific Algorithms using field programmable gate arrays (FPGAs) (Abstract Only) 15

An Automated Design Framework for Floating Point Scientific ...

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proceedings of the 2015 acm/sigda international symposium on field-programmable gate arrays

作者： Michaela E. Amoo Youngsoo Kim Vance Alford Shrikant Jadhav Naser I. El-Bathy Clay S. Gloster Jr. Howard University Washington DC USA North Carolina A&T State University Greensboro NC USA

ISBN: (纸本)9781450333153

This paper presents a reconfigurable computing environment while addressing the problem of porting High Performance Computing (HPC) applications directly to field programmable gate arrays (FPGAs)-based architectures. The objectives of this research are developing a comprehensive floating point library of essential functions for scientific applications; demonstrate order of magnitude speedup of reconfigurable computing applications, demonstrating the effectiveness of automated design framework for both development and test of scientific algorithms. The developed framework can be reused in various scientific applications which shares kernel functions. The study of this research has identified an exponential function as a kernel for cellular ophthalmoscopy camera processing, traffic monitoring and light wave simulation. The paper demonstrates 30x speedup of these kernels in three algorithms using its novel architecture and its automated toolset. Exponential kernel generation case study and its flexible hardware implementation on an FPGA has been validated onto a Xilinx LX-100 device and the Nallatech H101-PCIXM FPGA board.

关键词： floating point exponential hpc fpga

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Technology mapping for field-programmable gate arrays using integer programming 95

Technology mapping for field-programmable gate arrays using ...

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proceedings of the 1995 IEEE/acm international conference on Computer-aided design

作者： Amit Chowdhary John P. Hayes Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI

ISBN: (纸本)9780818672132

We show that the FPGA technology mapping problem can be efficiently implemented as a mixed integer linear programming (MILP) problem which generates truly optimal mappings. The MILP approach can handle a wide variety of FPGA logic block architectures. We present a compact MILP formulation for logic blocks based on lookup tables (LUTs) multiplexers. We also show that the MILP formulation can be easily modified to modified to optimize area, delay, or a combination of both. We demonstrate that moderately large benchmark circuits can be mapped in a reasonable time using the MILP approach directly. For larger circuits, we propose a technique of partitioning a circuit prior to mapping, which drastically reduces the computation time with little or no loss in optimality.

关键词： field-programmable gate arrays (FPGAs)

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QuickRec: Prototyping an intel architecture extension for record and replay of multithreaded programs 13

QuickRec: Prototyping an intel architecture extension for re...

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40th Annual international symposium on Computer Architecture, ISCA 2013

作者： Pokam, Gilles Danne, Klaus Pereira, Cristiano Kassa, Rolf Kranich, Tim Hu, Shiliang Gottschlich, Justin Honarmand, Nima Dautenhahn, Nathan King, Samuel T. Torrellas, Josep Intel Corporation United States University of Illinois Urbana-Champaign United States

ISBN: (纸本)9781450320795

There has been significant interest in hardware-assisted deterministic Record and Replay (RnR) systems for multithreaded programs on multiprocessors. However, no proposal has implemented this technique in a hardware prototype with full operating system support. Such an implementation is needed to assess RnR practicality. This paper presents QuickRec, the first multicore Intel Architecture (IA) prototype of RnR for multithreaded programs. QuickRec is based on QuickIA, an Intel emulation platform for rapid prototyping of new IA extensions. QuickRec is composed of a Xeon server platform with FPGA-emulated second-generation Pentium cores, and Capo 3, a full software stack for managing the recording hardware from within a modified Linux kernel. This paper's focus is understanding and evaluating the implementation issues of RnR on a real platform. Our effort leads to some lessons learned, as well as to some pointers for future research. We demonstrate that RnR can be implemented efficiently on a real multicore IA system. In particular, we show that the rate of memory log generation is insignificant, and that the recording hardware has negligible performance overhead. However, the software stack incurs an average recording overhead of nearly 13%, which must be reduced to enable always-on use of RnR. Copyright 2013 acm.

关键词： field programmable gate arrays (FPGA)

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Towards a hardware fault-injection testbed to support reproducible resiliency experiments

Towards a hardware fault-injection testbed to support reprod...

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2009 Workshop on Resiliency in High Performance, Resilience'09, Co-located with the 2009 international symposium on High Performance Distributed Computing Conference, HPDC'09

作者： Sass, Ron Sharma, Rahul R. DeBardeleben, Nathan Reconfigurable Computing Systems Lab. Univ. of N. Carolina at Charlotte 9201 University City Blvd. Charlotte NC 28223 United States Los Alamos National Laboratory MS B272 P. O. Box 1663 Los Alamos NM 87544 United States

ISBN: (纸本)9781605585932

As the largest computers in world continue to scale up to very large number of nodes, significant new problems emerge. Due to a number of different sources, hard and soft failures cause correctness issues and performance degradation in high component count machines. These issues simply do not occur at an appreciable rate in smaller scale machines. This presents a serious problem to researchers interested in studying and countering the issues because effects are not reproducible smaller scale testbeds. The Reconfigurable Computing Cluster (RCC) project is investigating the feasibility of using just FPGAs accelerators to build a high end computing computing system. However, since the hardware is very configurable, it is possible to also use this infrastructure to introduce special-purpose hardware cores that are designed to perturb or corrupt an existing system in a controlled way. This architecture offers an ideal platform for performing fault injections and "Heisenberg-free" monitoring of parallel programs. This work-in-progress describes several potential fault injectors and system monitors. A "bus cycle stealer" is demonstrated. This small hardware core can be programmed to wake up periodically and execute a variable number bus transactions. The effect on performance (single node and 16 node systems) are reported. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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A Reconfigurable Floating-Point Compliant Hardware Architecture for Neural Network Implementation 10

A Reconfigurable Floating-Point Compliant Hardware Architect...

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10th IEEE international symposium on Smart Electronic Systems, iSES 2024

作者： Yadav, Abhishek Dixit, Ayush Jana, Utsav Kumar, Binod IIT Jodhpur Dept. of EE Rajasthan India Singapore University of Technology & Design Singapore

ISBN: (纸本)9798331533229

Neural network architectures are increasingly pop-ular for their ability to perform fast and efficient compu-tations, leveraging inherent parallelism for quicker operation than conventional sequential methods. This paper presents a novel reconfigurable neural network architecture implemented with computationally less intensive hardware, along with a hardware accelerator-based design of a feed-forward neural network. The primary aim of this work is to optimize power and area utilization metrics using an approximate computing paradigm and a control unit that synchronizes the forward and backward passes. Moreover, in this paper, we introduce a compact and scalable hardware design approach for neural networks, validated through simulations and implementations on Xilinx Zynq and Zynq UltraScale+ MPSoC FPGA boards. Our architecture significantly reduces area overhead by 2.58 %, enhances power efficiency with an average power consumption of 110.67 mW, and achieves a 4.68-fold increase in throughput compared to software implementations. This improvement, while maintaining an average accuracy of around 91 % across different architectures, is due to the use of reconfigurable features and Padé-based optimization techniques. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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An efficient parallel yet pipelined reconfigurable architecture for M-PLN Weightless Neural Networks 14

An efficient parallel yet pipelined reconfigurable architect...

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27th symposium on Integrated Circuits and Systems Design, SBCCI 2014

作者： Da Silva, Felipe P. De Sa, Alan Oliveria Nedjahz, Nadia De Macedo Mourelle, Luiza Postgraduate Program of Electronics Engineering Faculty of Engineering State University of Rio de Janeiro Rio de Janeiro Brazil Dept. of Electronics Engineering and Telecommunications Faculty of Engineering State University of Rio de Janeiro Rio de Janeiro Brazil Brasil PCH Brazil Brazilian Navy Center of Elec-tronics Communications and Information Technology Rio de Janeiro RJ Brazil

ISBN: (纸本)9781479968732

Weightless Neural Networks (WNNs) are a powerful mechanism for pattern recognition. Aiming at enhancing their learning capabilities, Multivalued Probabilistic Logic Neurons (M-PLN) are used, instead of crisp neurons with a 0/1 output. An M-PLN bookkeeps a triggering probability for each input pattern to be recognized. The M-PLN model attempts to strengthen the discrepancies between distinct patterns used during the training process and those that have not yet been processed. In this paper, an efficient yet customizable hardware architecture for M-PLN based WNN is proposed. It implements the structure and learning process of a weightless pyramidal WNN, augmented by a probabilistic rewarding/punishing search algorithm. The training algorithm can adapt itself to the overall hit ratio so far achieved by the network. Using class-dedicated layers, the hardware is able to handle image classification in parallel and thus, very efficiently. Furthermore, the classification process is performed in a pipelined manner so its stages never stop working until all input images are classified. Nonetheless, only one of these layers is active during network training. Last but not least, the architecture is customizable as its structure can be tailored in accordance to the application characteristics. It was modeled and functionally tested. Estimated time requirements based on many simulations are reported. The architecture exhibits performance and reconfiguration capabilities that are very promising and encouraging towards the synthesis of a prototype. © 2014 IEEE.

关键词： field programmable gate arrays (FPGA)

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Future design tools for platform FPGAs 03

Future design tools for platform FPGAs

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symposium on Integrated Circuits and Systems Design (SBCCI)

作者： P. Lysaght Xilinx Research Laboratories CA USA

ISBN: (纸本)9780769520094

According to current projections, programmable platforms will dominate ASIC design starts as the semiconductor industry moves to 90 nm process technology and beyond. In this paper, we assess the implications of this trend and explore the impact it will have on system-level design methodologies for FPGAs. We review current research and practice in system-level design and attempt to assess how much of the ASIC experience will be relevant to future FPGA designers.

关键词： field programmable gate arrays Application specific integrated circuits System-level design Concurrent computing Electronics industry Costs Digital signal processing Embedded software Logic design Silicon

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Are FPGAs suffering from the innovator's dilemna? 13

Are FPGAs suffering from the innovator's dilemna?

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proceedings of the acm/sigda international symposium on field programmable gate arrays

作者： Vaughn Betz Jason Cong University of Toronto Toronto ON Canada UCLA Los Angeles CA USA

ISBN: (纸本)9781450318877

FPGAs constitute a highly profitable industry, with approximately $5 billion of sales per year. High barriers to entry keep most companies away, and enable high profit margins for the incumbents. The industry has grown greatly over the years, but still constitutes a small portion of the overall semiconductor market. This raises the question to be addressed by this panel: is the FPGA community innovating as much as it should, or is a bias to maintain high profit margins and protect the cash flow of the current FPGA market holding us back from exploring new ideas and products that could greatly expand the appeal of and market for FPGA-related technology? This would be a classic case of the innovator's dilemma defined by Clayton Christensen: it is difficult for a company to engage in creative destruction of a cash cow *** distinguished panel of experts will discuss whether we are seeing major innovation in architectures, design flows and applications, or only incremental improvements. We will also discuss if any new (possibly low margin) application domain is left out by the FPGA industry, what radical ideas should be explored, and whether large incumbents, new startups, academia or some combination are best able to attack these new areas.

关键词： field programmable gate arrays

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HexCell: a Hexagonal Cell for Evolvable Systolic arrays on FPGAs: (Abstract Only) 18

HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on F...

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proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Fady Hussein Luka Daoud Nader Rafla Boise State University Boise ID USA

ISBN: (纸本)9781450356145

This paper presents a novel cell architecture for evolvable systolic arrays. HexCell is a tile-able processing element with a hexagonal shape that can be implemented and dynamically reconfigured on field-programmable gate arrays (FPGAs). The cell contains a functional unit, three input ports, and three output ports. It supports two concurrent configuration schemes: dynamic partial reconfiguration (DPR), where the functional unit is partially reconfigured at run time, and virtual reconfiguration circuit (VRC), where the cell output port bypasses one of the input data or selects the functional unit output. Hence, HexCell combines the merits of DPR and VRC including resource-awareness, reconfiguration speed and routing flexibility. In addition, the cell structure supports pipelining and data synchronization for achieving high throughput for data-intensive applications like image processing. A HexCell is represented by a binary string (chromosome) that encodes the cell's function and the output selections. Our developed evolvable HexCell array supports more inputs and outputs, a variety of possible datapaths, and has faster reconfiguration, compared to the state-of-the-art systolic array while maintaining the same resource utilization. Moreover, by using the same genetic algorithm on the two systolic arrays, results show that the HexCell array has higher throughput and can evolve faster than state-of-the-art array.

关键词： fpga hexcell systolic arrays dynamic partial reconfiguration (dpr) evolvable hardware virtual reconfiguration circuit (vrc)

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