检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

765 篇 会议
30 篇 期刊文献

馆藏范围

795 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

631 篇 工学
- 583 篇 计算机科学与技术...
- 345 篇 软件工程
- 267 篇 电子科学与技术（可...
- 186 篇 电气工程
- 109 篇 信息与通信工程
- 42 篇 控制科学与工程
- 41 篇 动力工程及工程热...
- 29 篇 机械工程
- 20 篇 生物工程
- 13 篇 建筑学
- 12 篇 仪器科学与技术
- 11 篇 冶金工程
- 11 篇 土木工程
- 9 篇 材料科学与工程（可...
- 9 篇 化学工程与技术
- 9 篇 生物医学工程（可授...
- 4 篇 光学工程
- 4 篇 农业工程
235 篇 理学
- 192 篇 数学
- 39 篇 物理学
- 21 篇 生物学
- 20 篇 统计学（可授理学、...
- 11 篇 系统科学
- 7 篇 化学
66 篇 管理学
- 55 篇 管理科学与工程(可...
- 36 篇 工商管理
- 12 篇 图书情报与档案管...
18 篇 经济学
- 18 篇 应用经济学
16 篇 法学
- 14 篇 社会学
4 篇 教育学
- 4 篇 教育学
4 篇 农学

主题

357 篇 field programmab...
241 篇 field programmab...
37 篇 signal processin...
36 篇 clocks
34 篇 ofdm
34 篇 estimation
33 篇 modulation
33 篇 filtration
30 篇 fpga
22 篇 hardware
17 篇 routing
15 篇 computer archite...
14 篇 switches
13 篇 table lookup
11 篇 logic arrays
11 篇 prototypes
10 篇 systolic arrays
10 篇 costs
9 篇 field-programmab...
9 篇 field-programmab...

机构

6 篇 univ of toronto ...
6 篇 imperial college...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 xilinx
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 university of ca...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 department of co...
3 篇 school of comput...

作者

21 篇 cong jason
20 篇 rose jonathan
12 篇 betz vaughn
10 篇 hauck scott
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
8 篇 chen deming
8 篇 langhammer marti...
7 篇 constantinides g...
7 篇 chow paul
6 篇 anderson jason h...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
5 篇 jason cong
5 篇 so hayden kwok-h...
5 篇 dehon andre

语言

784 篇 英文
11 篇 其他

检索条件"任意字段=Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 795 条记录，以下是721-730 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Multiple FPGA Partitioning with Performance Optimization

Multiple FPGA Partitioning with Performance Optimization

引用

proceedings of the acm international symposium on field-programmable gate arrays, FPGA

作者： K. Roy-Neogi C. Sechen Department of Electrical Engineering University of Washington Seattle WA USA

We address the problem of partitioning a technology mapped FPGA circuit onto multiple FPGAs of a specific target technology. The physical characteristics of the multiple FPGA system (MFS) pose additional constraints to the circuit partitioning algorithms: the capacity of each FPGA, the timing constraints, the number of I/Os per FPGA, and the pre-designed interconnection patterns of the MFS. Existing partitioning techniques which minimize just the cut sizes of partitions fail to satisfy the above challenges. We therefore present a rectilinear partitioning algorithm which efficiently and accurately handles timing specifications. The signal path delays are estimated during partitioning using a timing model specific to a multiple FPGA architecture. The model combines all possible delay factors in a system with multiple FPGA chips of a target technology. A new dynamic net-weighting scheme was incorporated to minimize the number of pin-outs for each chip. Finally, we have developed a graph-based global router for pin assignment which can handle the pre-routed connections of our MFS structure. We successfully partitioned the MCNC Xilinx FPGA benchmarks producing 100% routable designs with high utilization levels in all cases. Using the performance optimization capabilities in our approach we have successfully partitioned these benchmarks satisfying the critical path constraints and achieving a significant reduction in the longest path delay. An average reduction of 17% in the longest path delay was achieved at the cost of 5% in total wire length. We have proved the effectiveness of our performance optimization technique by verifying the timing predictions of our partitioner with the actual delays obtained after placement and routing of a partitioned MFS. Partitioning results obtained with the Xilinx mapped MCNC benchmarks are encouraging.

关键词： field programmable gate arrays Optimization Timing Partitioning algorithms Delay estimation Integrated circuit interconnections Costs Wire Delay effects Routing

来源：评论

学校读者我要写书评

暂无评论

Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity 19

Embracing Systolic: Super Systolization of Large-Scale Circu...

引用

proceedings of the 2019 acm/sigda international symposium on field-programmable gate arrays

作者： Jiafeng Xie Chiou-Yng Lee Villanova University Villanova PA USA Lunghwa University of Science and Technology Taoyuan Taiwan Roc

ISBN: (纸本)9781450361378

The recent advance in artificial intelligence (AI) technology has led to a new round of systolic structure innovation. Many AI accelerators have employed systolic structure to realize the core large-scale matrix-vector multiplication for high-performance processing, which has a complexity of $o(n^2)$ for matrix size of $n\times n$ (difficult to be implemented on the field-programmable gate array (FPGA) platform). To overcome this drawback, in this paper, we propose a super systolization strategy to implement the core circulant matrix-vector multiplication into a systolic structure with subquadratic space complexity. The proposed effort is carried out through two stages of coherent interdependent efforts: (i) a novel matrix-vector multiplication algorithm based on Toeplitz matrix-vector product (TMVP) approach is proposed to obtain subquadratic space complexity; (ii) a series of optimization techniques are introduced to map the proposed algorithm into desired systolic structure. Finally, detailed complexity analysis and comparison have been conducted to prove the efficiency of the proposed strategy. The proposed strategy is highly efficient and can be extended in many neural network based hardware implementation platforms.

关键词： field-programmable gate array systolic structure large-scale toeplitz matrix vector product circulant matrix-vector multiplication subquadratic space complexity

来源：评论

学校读者我要写书评

暂无评论

Design and Implementation of a Primary Visual Cortex Pathway Model Based on Opponent-process Theory 24

Design and Implementation of a Primary Visual Cortex Pathway...

引用

proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Hui Wei Jingyong Ye Yutong Chen Heng Wu Fudan University Shanghai China University of Science and Technology of China Hefei China

ISBN: (纸本)9798400704185

Neurobiology has made groundbreaking discoveries that have propelled the development of brain-inspired computing. This new field of research has led to the creation of neural pathways that mirror the human brain's visual system, providing numerous transformative insights for modern image processing. Brain-like vision offers remarkable processing efficiency and promises a range of exciting applications, from enhancing video surveillance to improving medical diagnosis. However, current brain-inspired computing models lack portability and efficient power consumption, which limits their widespread use. To address these challenges, we've designed a brain-like color opponent multi-layer neural network model on field programmable gate arrays (FPGAs). This innovative approach enhances portability, reduces power consumption, and increases parallelism in the brain-like computational model. We've conducted rigorous experiments on natural images, and the results are promising. FPGAs can further enhance this innovative approach by improving computational parallelism and enhancing the display of crucial structural information while downplaying trivial details. This integration of biological mechanisms into practical embedded systems is a significant step towards merging these two technologies. Our multi-layer neural network structure aligns with FPGAs' in-memory computing mechanism, bridging the gap between these two technologies. Our work represents a step towards merging them and utilizes physiological color opponent theory to enhance FPGAs' effectiveness in practical image processing applications. By combining the power of neurobiology with the flexibility of FPGAs, we can create more efficient and practical solutions for image processing tasks in various fields.

关键词： brain-like vision neurovisual pathways opponent-process programmable devices

来源：评论

学校读者我要写书评

暂无评论

The design of a low energy FPGA 99

The design of a low energy FPGA

引用

international symposium on Low Power Electronics and Design (ISLPED)

作者： V. George Hui Zhang J. Rabaey Berkeley Wireless Research Center University of California Berkeley CA USA

ISBN: (纸本)9781581131338

This work presents the design of an energy efficient FPGA architecture. Significant reduction in the energy consumption is achieved by tackling both circuit design and architecture optimization issues concurrently. A hybrid interconnect structure incorporating nearest neighbor connections, symmetric mesh architecture, and hierarchical connectivity is used. The energy of the interconnect is also reduced by employing low-swing circuit techniques. These techniques have been employed to design and fabricate an FPGA. Preliminary analysis show energy improvement of more than an order of magnitude when compared to existing commercial architectures.

关键词： field programmable gate arrays Integrated circuit interconnections Computer architecture Power dissipation Energy efficiency Energy consumption Clocks Frequency Logic Switches

来源：评论

学校读者我要写书评

暂无评论

FPGA implementation of highly parallelized decoder logic for network coding (abstract only) 10

FPGA implementation of highly parallelized decoder logic for...

引用

proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Sunwoo Kim Won W. Ro Yonsei University Seoul South Korea

ISBN: (纸本)9781605589114

Decoding operation is one of the major performance bottlenecks in network coding applications. To address the problem caused by decoding delay, this paper proposes high-performance decoding logic on the field-programmable gate-array (FPGA). A Galois field arithmetic logic unit (GF ALU) is implemented with a full parallelization. We claim that the complexity of hardware is reduced by use of the log and anti-log tables. In addition, the fast arithmetic operation is achieved by the parallelized GF ALU architecture, which allows one-row-calculations of a matrix to be performed concurrently. The decoders for four different sizes of the coefficient matrix have been implemented while the degree of parallelism is preserved for each size. The performance is evaluated by comparing with the performance of the decoding operation both on the ARM processor emulator and a real ARM processor. Using a modern Xilinx Virtex-5 device, the decoding time of 3.5 ms for the size 16 x 16 and 190.5 ms for 128 x 128 has been achieved at the operating frequency of 50MHz, which is equal to 12.7 and 21.7 in terms of speedup.

关键词： network coding fpga fpga implementation galois field arithmetic

来源：评论

学校读者我要写书评

暂无评论

Diagnosing programmable interconnect systems for FPGAs 96

Diagnosing programmable interconnect systems for FPGAs

引用

proceedings of the 1996 acm fourth international symposium on field-programmable gate arrays

作者： Fabrizio Lombardi David Ashen Xiaotao Chen Wei Kang Huang Department of Computer Science Texas A&M University College Station TX Dept. of Electronic Engineering Fudan University Shanghai 200433 P.R. China

No abstract available.

ISBN: (纸本)9780897917735

No abstract available.

关键词：

来源：评论

学校读者我要写书评

暂无评论

A programmable majority logic array using molecular scale electronics 06

A programmable majority logic array using molecular scale el...

引用

proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Garrett S. Rose Mircea R. Stan University of Virginia Charlottesville VA

ISBN: (纸本)9781595932921

We present a computer architecture design that utilizes molecular electronic devices fabricated from self-assembled monolayers (SAM) of molecules. This architecture has been designed for a process being developed at the University of Virginia where molecules are assembled via vapor phase deposition. As this process lends itself nicely to developing multiple layers of devices on a single substrate, the circuit and architectural designs presented here exist in three dimensions. Through this work we show how molecular electronics naturally allows for 3D integration at the *** design consists of two types of molecular devices: switches with memory and resonant tunneling diodes (RTD). These switching molecules are patterned between layers of metal to form a uniform crossbar array that can behave similar to a programmable logic array (PLA). In this design, the crossbar arrays drive rows of circuits, referred to as Goto pairs, consisting of two stacked molecular RTDs. As described in previous work, a Goto pair with only one resistor driving its input functions as a latch whereas the circuit acts as a majority gate when driven by multiple resistors. Since the crossbar arrays can be programmed such that the various Goto pairs are driven by different numbers of inputs, the overall circuit has the ability to implement logic as networks of latches and majority gates. Using crossbar arrays in this way is somewhat different from other approaches in that logic is not simply implemented in the array but is a product of both the array and the Goto pair functionality.

关键词：

来源：评论

学校读者我要写书评

暂无评论

CReconfigurable finite field instruction set architecture 07

CReconfigurable finite field instruction set architecture

引用

proceedings of the 2007 acm/sigda 15th international symposium on field programmable gate arrays

作者： Nathan Jachimie Fernando Martinez-Vallin Jafar Saniie Illinois Institute of Technology Chicago Illinois

ISBN: (纸本)9781595936004

Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite field instruction set extensions and a reconfiguration framework have been constructed to enable a finite field multiplier to be regenerated via software control. A performance evaluation has been created by generating a Finite field Extensions Unit with MicroBlaze processor in a Xilinx Virtex2Pro FPGA. By utilizing the in-system partial reconfiguration capability, the finite field multiplier can be customized to a particular size and definition. With a customized GF(2163 ) multiplier, a speed-up factor of 1530X has been demonstrated versus execution of the same algorithm on the MicroBlaze processor alone.

关键词： FSL instruction set extensions Xilinx fast simplex links galois fields MicroBlaze embedded development partial reconfiguration finite field arithmetic

来源：评论

学校读者我要写书评

暂无评论

[email protected] all-programmable SoC ecosystem 14

[email protected] all-programmable SoC ecosystem

引用

proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Antonio Filgueras Eduard Gil Daniel Jimenez-Gonzalez Carlos Alvarez Xavier Martorell Jan Langer Juanjo Noguera Kees Vissers Barcelona Supercomputing Center - BSC-CNS Barcelona Spain Universitat Politecnica de Catalunya - UPC Barcelona Spain Xilinx Inc. Dublin Ireland Xilinx inc. San Jose CA USA

ISBN: (纸本)9781450326711

OmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely influenced the recently appeared OpenMP 4.0 specification. Zynq All-programmable SoC combines the features of a SMP and a FPGA and benefits DLP, ILP and TLP parallelisms in order to efficiently exploit the new technology improvements and chip resource capacities. In this paper, we focus on programmability and heterogeneous execution support, presenting a successful combination of the OmpSs programming model and the Zynq All-programmable SoC platforms.

关键词： task dataflow models automatic hardware generation framework heterogenous parallel programming model

来源：评论

学校读者我要写书评

暂无评论

DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only) 18

DATuner: An Extensible Distributed Autotuning Framework for ...

引用

proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Gai Liu Ecenur Ustun Shaojie Xiang Chang Xu Guojie Luo Zhiru Zhang Cornell University Ithaca NY USA IBM Research China Beijing China Peking University Beijing China

ISBN: (纸本)9781450356145

Mainstream FPGA tools contain an extensive set of user-controlled compilation options and internal optimization strategies that significantly impact the design quality. These compilation and optimization parameters create a complex design space that human designers may not be able to effectively explore in a time-efficient manner. In this work we describe DATuner, an open-source extensible distributed autotuning framework for optimizing FPGA designs and design automation tools using an ensemble of search techniques managed by multi-armed bandit algorithms. DATuner is designed for a distributed environment that uses parallel searches to amortize the significant runtime overhead of the CAD tools. DATuner provides convenient interface for extension to user-supplied tools, which enables the end users to apply DATuner to design tools/flows of their interest. We demonstrate the effectiveness and extensibility of DATuner using three case studies, which include clock frequency optimization for FPGA compilation, fixed-point optimization, and autotuning logic synthesis transformations.

关键词： field-programmable gate array design automation distributed autotuning

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共80页 << < 69 70 71 72 73 74 75 76 77 78 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：