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DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only) 18

DATuner: An Extensible Distributed Autotuning Framework for ...

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proceedings of the 2018 acm/sigda international symposium on field-programmable gate arrays

作者： Gai Liu Ecenur Ustun Shaojie Xiang Chang Xu Guojie Luo Zhiru Zhang Cornell University Ithaca NY USA IBM Research China Beijing China Peking University Beijing China

ISBN: (纸本)9781450356145

Mainstream FPGA tools contain an extensive set of user-controlled compilation options and internal optimization strategies that significantly impact the design quality. These compilation and optimization parameters create a complex design space that human designers may not be able to effectively explore in a time-efficient manner. In this work we describe DATuner, an open-source extensible distributed autotuning framework for optimizing FPGA designs and design automation tools using an ensemble of search techniques managed by multi-armed bandit algorithms. DATuner is designed for a distributed environment that uses parallel searches to amortize the significant runtime overhead of the CAD tools. DATuner provides convenient interface for extension to user-supplied tools, which enables the end users to apply DATuner to design tools/flows of their interest. We demonstrate the effectiveness and extensibility of DATuner using three case studies, which include clock frequency optimization for FPGA compilation, fixed-point optimization, and autotuning logic synthesis transformations.

关键词： field-programmable gate array design automation distributed autotuning

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SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays 98

SMAP: heterogeneous technology mapping for area reduction in...

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proceedings of the 1998 acm/sigda sixth international symposium on field programmable gate arrays

作者： Steven J. E. Wilton Department of Electrical and Computer Engineering University of British Columbia Vancouver BC Canada V6T 1Z4

ISBN: (纸本)9780897919784

It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for customers that do not use all of the storage provided. This chip area need not be wasted, and can in fact be used very efficiently, if the arrays are configured as large multi-output ROMs, and used to implement *** order to efficiently use the embedded arrays in this way, a technology mapping algorithm that identifies parts of circuits that can be efficiently mapped to an embedded array is required. In this paper, we describe such an algorithm. The new tool, called SMAP, packs as much circuit information as possible into the available memory arrays, and maps the rest of the circuit into four-input lookup-tables. On a set of 29 sequential and combinational benchmarks, the tool is able to map, on average, 60 4-LUTs into a single 2-Kbit memory array. If there are 16 arrays available, it can map, on average, 358 4-LUTs to the 16 arrays.

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FPGA-based fine-grain parallel computing (abstract only) 11

FPGA-based fine-grain parallel computing (abstract only)

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proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Andrew W. Hill Andrea Di Blas Richard Hughey University of California Santa Cruz Santa Cruz CA USA

ISBN: (纸本)9781450305549

FPGAs are increasing in computing power at a significant rate while the non-recurring engineering costs and time-to-market remain significant lower than those for application-specific integrated circuits (ASICs), encouraging FPGAs to be used in areas previous dominated by ASICs. In this study, we examine the appropriateness of FPGAs for high-performance, low-volume prodution parallel computing by mapping an existing ASIC-based massively parallel single-instruction, multiple data (SIMD) computer, the UCSC Kestrel, to a variety of FPGAs. The design has a raw peak performance of over 187 billion 8-bit operations per second (OPS), 48 times faster than the original ASIC-based Kestrel, using a Xilinx Virtex-6, and a cost efficiency of up to 81 MOPS/$ using a Xilinx Spartan-3. We also show that we can implement the entire original Kestrel (512 processing elements) as a system on a single programmable chip.

关键词： system on a programmable chip simd parallel computing

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The design of RPM: an FPGA-based multiprocessor emulator 95

The design of RPM: an FPGA-based multiprocessor emulator

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proceedings of the 1995 acm third international symposium on field-programmable gate arrays

作者： Koray Öner Luiz A. Barroso Sasan Iman Jaeheon Jeong Krishnan Ramamurthy Michel Dubois Department of Electrical Engineering - Systems University of Southern California Los Angeles CA

ISBN: (纸本)9780897917438

Recent advances in field-programmable gate arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improvements in Computer-Aided Design (CAD) tools, mainly in synthesis tools, greatly simplify the design of large circuits. The RPM (Rapid Prototype Engine for Multiprocessors) Project leverages these two technological advances. Its goal is to develop a common hardware platform for the emulation of multiprocessor systems with different *** cost reasons, the use of FPGAs in RPM is limited to the memory controllers, while the rest of the emulator, including the processors, memories and interconnect, is built with off-the-shelf components. A flexible non-intrusive event logging mechanism is included at all levels of the memory hierarchy, making it possible to monitor the emulation in very fine detail. This paper presents the hardware design of RPM.

关键词： rapid prototyping field-programmable gate arrays shared-memory multiprocessors logic emulation message-passing multicomputers

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From high-level deep neural models to FPGAS 49

From high-level deep neural models to FPGAS

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49th Annual IEEE/acm international symposium on Microarchitecture, MICRO 2016

作者： Sharma, Hardik Park, Jongse Mahajan, Divya Amaro, Emmanuel Kim, Joon Kyung Shao, Chenkai Mishra, Asit Esmaeilzadeh, Hadi Lab School of Computer Science Georgia Institute of Technology United States Intel Corporation United States

ISBN: (纸本)9781509035083

Deep Neural Networks (DNNs) are compute-intensive learning models with growing applicability in a wide range of domains. FPGAS are an attractive choice for DNNs since they offer a programmable substrate for acceleration and are becoming available across different market segments. However, obtaining both performance and energy efficiency with FPGAS is a laborious task even for expert hardware designers. Furthermore, the large memory footprint of DNNs, coupled with the FPGAS' limited on-chip storage makes DNN acceleration using FPGAS more challenging. This work tackles these challenges by devising DnnWeaver, a framework that automatically generates a synthesizable accelerator for a given (DNN, FPGA) pair from a high-level specification in Caffe [1]. To achieve large benefits while preserving automation, DNNWEAVER generates accelerators using hand-optimized design templates. First, DnnWeaver translates a given high-level DNN specification to its novel ISA that represents a macro dataflow graph of the DNN. The DnnWeaver compiler is equipped with our optimization algorithm that tiles, schedules, and batches DNN operations to maximize data reuse and best utilize target FPGA's memory and other resources. The final result is a custom synthesizable accelerator that best matches the needs of the DNN while providing high performance and efficiency gains for the target FPGA. We use DnnWeaver to generate accelerators for a set of eight different DNN models and three different FPGAS, Xilinx Zynq, Altera Stratix V, and Altera Arria 10. We use hardware measurements to compare the generated accelerators to both multicore CPUs (ARM Cortex A15 and Xeon E3) and many-core GPUs (Tegra K1, GTX 650Ti, and Tesla K40). In comparison, the generated accelerators deliver superior performance and efficiency without requiring the programmers to participate in the arduous task of hardware design. © 2016 IEEE.

关键词： field programmable gate arrays (FPGA)

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Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the international Space Station 23

Fault Detection on Multi COTS FPGA Systems for Physics Exper...

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proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Tim Oberschulte Jakob Marten Holger Blume Gottfried Wilhelm Leibniz University Hannover Hannover Germany

ISBN: (纸本)9781450394178

field-programmable gate arrays (FPGAs) in space applications come with the drawback of radiation effects, which inevitably will occur in devices of small process size. This also applies to the electronics of the Bose Einstein Condensate and Cold Atom Laboratory (BECCAL) apparatus, which is planned to operate on the international Space Station for several years. A total of more than 100 FPGAs distributed in the setup will be used for high-precision control of specialized sensors and actuators at nanosecond scale. Due to the large amount of devices in BECCAL, commercial off-the-shelf (COTS) FPGAs are used which are not radiation hardened. In this work, we detect and mitigate radiation effects in an application specific COTS-FPGA-based communication network. For that redundancy is integrated into the design while the firmware is optimized to stay within the FPGA's resource constraints. A redundant integrity checker module is developed which can notify preceding network devices about data and configuration bit errors. The firmware is evaluated by injecting faults into data and configuration registers in simulation and real hardware. The FPGA resource usage of the firmware is cut down by more than half, enabling the use of double modular redundancy for the switching fabric. Together with the triple modular redundancy protected integrity checker, this combination fully prevents silent data corruptions in the design as shown in simulations and by injecting faults in hardware using the Intel Fault Injection FPGA IP Core while staying in the resource limitation of a COTS FPGA.

关键词： fault detection commercial off-the-shelf space application

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LiquidMD: Optimizing Inter-die and Intra-die placement for 2.5D FPGA Architectures 14

LiquidMD: Optimizing Inter-die and Intra-die placement for 2...

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14th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2024

作者： Raikar, Raveena Stroobandt, Dirk Ghent University Belgium

ISBN: (纸本)9798400717277

Interposer-based 2.5D FPGAs contain multiple dies interconnected through external wires. While essential for increasing capacity, these external connections introduce higher delays and longer wirelengths. Efficient placement tools are needed for such architecture to strategically manage signal counts at the die boundary. Previous research on 2.5D FPGA placement has often relied on global placement optimization, which, while effective, can be time-consuming and scales poorly with larger designs. Leveraging the modularity of 2.5D systems and the configuration of the interposer interface, we propose a novel approach to incorporating die-level parallelism that requires less global optimization. Our methodology employs netlist partitioning and introduces virtual anchor blocks to enable parallel placement of subcircuits on each die. We introduce a streamlined synchronization strategy for optimizing inter-partition nets. This methodology is integrated into the multi-die placement tool, g LiquidMD', resulting in an enhanced parallelized version of the tool. Comparison of our base multi-die placer with a state-of-The-Art tool that fully globally optimizes the placement demonstrates a significant runtime improvement without compromising placement quality. Additionally, we assess our partial synchronization technique in contrast to a placement strategy with no synchronization and observe improved critical path delay. Subsequently, we explore the synchronization process in-depth to assess how the placement can derive advantages from minimal synchronization. We initially evaluate the suitable position for introducing synchronization in the tool flow, followed by an assessment of the required synchronization frequency in the tool flow. Our research sheds light on determining the optimal balance between parallelism and synchronization in 2.5D FPGA placement, culminating in a modular placement algorithm that strikes a favourable balance between runtime efficiency and placement qual

关键词： field programmable gate arrays (FPGA)

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A field-programmable mixed-analog-digital array 95

A field-programmable mixed-analog-digital array

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proceedings of the 1995 acm third international symposium on field-programmable gate arrays

作者： Paul Chow P. Glenn Gulak Department of Electrical and Computer Engineering University of Toronto Toronto Ontario Canada M5S 1A4

ISBN: (纸本)9780897917438

A novel field-programmable mixed-analog-digital array (FPMA) is proposed, which contains a field-programmable analog array, a field-programmable digital array, and a mixed-signal interface. This device is intended to be used for the rapid implementation of mixed-signal circuits. The resource and architectural requirements for this array are determined by analyzing a set of sample circuits. The mixed-signal interface is constructed from converter blocks that contain configurable A/D and D/A converters, which gives some flexibility in the specification of the interface. A 1.2 μm CMOS prototype IC has been designed to demonstrate the feasibility of FPMA technology.

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Methodology to generate multi-dimensional systolic arrays for FPGAs using openCL (abstract only) 14

Methodology to generate multi-dimensional systolic arrays fo...

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proceedings of the 2014 acm/sigda international symposium on field-programmable gate arrays

作者： Nick Ni Embedded Applications Engineer Altera Corporation San Jose CA USA

ISBN: (纸本)9781450326711

Systolic arrays (SA) in a FPGA provide a significant speed up on many scientific calculations through massive parallelism exploitation. The low-level hardware design of such complex SA is becoming more time-consuming and non-scalable with more transistors being available on a single chip. In this paper we present a novel methodology to generate multi-dimensional SA for FPGAs using a well-accepted high-level language, OpenCL. Kernels written in OpenCL can then be compiled directly into hardware using an OpenCL high-level synthesis tool. A complex case study using our methodology is presented. We were able to design, generate, verify and optimize the entire FPGA based hardware accelerator using the Smith-Waterman, in only three man weeks. The accelerator's top performance was 32.6 GCUPS (Giga-Cell-Updates-Per-Second) on a DNA similarity search with 1.3 GCUPS/watt efficiency. The result is superior to most state-of-the-art CPU/GPU implementations and competitive against a hand-crafted hardware design which took many months to develop.

关键词： high-level synthesis bioinformatics productivity smith-waterman opencl fpga systolic arrays generation algorithm

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Stochastic-Based Spin-programmable gate Array with Emerging MTJ Device Technology (Abstract Only) 16

Stochastic-Based Spin-Programmable Gate Array with Emerging ...

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proceedings of the 2016 acm/sigda international symposium on field-programmable gate arrays

作者： Yu Bai Mingjie Lin University of Central Florida Orlando FL USA

ISBN: (纸本)9781450338561

This paper describes the stochastic-based Spin-programmable gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in FPGAs, our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure. Our mixed mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10x improvement in logic density, about 5x improvement in average net delay, and about 5x improvement in the critical path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits.

关键词： stochastic fpga emerging devices

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