检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

765 篇 会议
30 篇 期刊文献

馆藏范围

795 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

631 篇 工学
- 583 篇 计算机科学与技术...
- 345 篇 软件工程
- 267 篇 电子科学与技术（可...
- 186 篇 电气工程
- 109 篇 信息与通信工程
- 42 篇 控制科学与工程
- 41 篇 动力工程及工程热...
- 29 篇 机械工程
- 20 篇 生物工程
- 13 篇 建筑学
- 12 篇 仪器科学与技术
- 11 篇 冶金工程
- 11 篇 土木工程
- 9 篇 材料科学与工程（可...
- 9 篇 化学工程与技术
- 9 篇 生物医学工程（可授...
- 4 篇 光学工程
- 4 篇 农业工程
235 篇 理学
- 192 篇 数学
- 39 篇 物理学
- 21 篇 生物学
- 20 篇 统计学（可授理学、...
- 11 篇 系统科学
- 7 篇 化学
66 篇 管理学
- 55 篇 管理科学与工程(可...
- 36 篇 工商管理
- 12 篇 图书情报与档案管...
18 篇 经济学
- 18 篇 应用经济学
16 篇 法学
- 14 篇 社会学
4 篇 教育学
- 4 篇 教育学
4 篇 农学

主题

357 篇 field programmab...
241 篇 field programmab...
37 篇 signal processin...
36 篇 clocks
34 篇 ofdm
34 篇 estimation
33 篇 modulation
33 篇 filtration
30 篇 fpga
22 篇 hardware
17 篇 routing
15 篇 computer archite...
14 篇 switches
13 篇 table lookup
11 篇 logic arrays
11 篇 prototypes
10 篇 systolic arrays
10 篇 costs
9 篇 field-programmab...
9 篇 field-programmab...

机构

6 篇 univ of toronto ...
6 篇 imperial college...
5 篇 university of to...
5 篇 univ of toronto
5 篇 univ of californ...
5 篇 altera corporati...
4 篇 univ british col...
4 篇 dept. of cs 256-...
4 篇 department of el...
4 篇 xilinx
4 篇 intel corporatio...
3 篇 computer science...
3 篇 tsinghua univers...
3 篇 university of ca...
3 篇 department of ee...
3 篇 georgia inst tec...
3 篇 department of el...
3 篇 xilinx inc. san ...
3 篇 department of co...
3 篇 school of comput...

作者

21 篇 cong jason
20 篇 rose jonathan
12 篇 betz vaughn
10 篇 hauck scott
10 篇 wawrzynek john
9 篇 dehon andré
9 篇 zhang zhiru
8 篇 wilton steven j....
8 篇 schmit herman
8 篇 chen deming
8 篇 langhammer marti...
7 篇 constantinides g...
7 篇 chow paul
6 篇 anderson jason h...
6 篇 wilton steven j....
6 篇 pasca bogdan
6 篇 li fei
5 篇 jason cong
5 篇 so hayden kwok-h...
5 篇 dehon andre

语言

784 篇 英文
11 篇 其他

检索条件"任意字段=Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays"

共 795 条记录，以下是71-80 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Effect of LUT and cluster size on deep-submicron FPGA performance and density

Effect of LUT and cluster size on deep-submicron FPGA perfor...

引用

FPGA 2000: acm/sigda international symposium on field programmable gate arrays

作者： Ahmed, Elias Rose, Jonathan Univ of Toronto Toronto Ont Canada

The FPGA architectural issue of the effect of logic block functionality on FPGA performance and density is investigated. In particular, in the context of lookup tables (LUT), cluster-based island-style FPGAs, the effect of LUT size and cluster size on the speed and logic density of an FPGA is analyzed. A fully timing-driven experimental flow, in which a set of benchmark circuits are synthesized, is used into different cluster based logic book architectures, which contain groups of LUTs and flip-flops.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Clock power reduction for virtex-5 FPGAs

Clock power reduction for virtex-5 FPGAs

引用

7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Wang, Qiang Gupta, Subodh Anderson, Jason Xilinx Inc. Logic Drive San Jose CA 95124 United States ECE Dept Univ. of Toronto King's College Road Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781605584102

Clock network power in field-programmable gate arrays (FP- ) is considered and two complementary approaches for power reduction in the Xilinx RVirtexTM-5 FPGA are. The approaches are unique in that they lever- specific architectural aspects of Virtex-5 to achieve re- in dynamic power consumed by the clock network. first approach comprises a placement-based technique reduce interconnect resource usage on the clock network, reducing capacitance and power (up to 12%). The approach borrows the "clock gating" notion from the domain and applies it to FPGAs. Clock enable sig- on flip-flops are selectively migrated to use the dedi- clock enable available on the FPGA's built-in clock, leading to reduced toggling on the clock intercon- and lower power (up to 28%). Power reductions are achieved without any performance penalty, on average. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Evaluation of low-leakage design techniques for field programmable gate arrays

Evaluation of low-leakage design techniques for field progra...

引用

acm/sigda Twelfth acm international symposium on field-programmable gate arrays - FPGA 2004

作者： Rahman, Arifur Polavarapuv, Vijay Department of Electrical Engineering Polytechnic University Brooklyn NY 11201 United States

In this paper we evaluate the trade-offs between various low-leakage design techniques for field programmable gate arrays (FGPAs) in deep sub-micron technologies. Since multiplexers are widely used in FPGAs for implementing look up tables (LUTs) and connection and routing switches, several low-leakage implementations of pass transistor based multiplexers and routing switches are proposed and their design trade-offs are presented based on transistor-level simulation, physical design, and impact on overall system performance. We find that gate biasing, the use of redundant SRAM cells, and integration of multi-Vt technology are ideal for FPGAs, and they can reduce leakage current by 2X-4X compared to an implementation without any leakage reduction technique. For some of the potential low-leakage design techniques being evaluated in our study, the impact on chip area is very minimal to an increase of 15% - 30%.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Architectural Improvements for field programmable Counter arrays: Enabling Efficient Synthesis of Fast Compressor Trees on FPGAs 08

Architectural Improvements for Field Programmable Counter Ar...

引用

16th acm/sigda international symposium on field-programmable gate arrays

作者： Cevrero, Alessandro Athanasopoulos, Panagiotis Parandeh-Afshar, Hadi Verma, Ajay K. Brisk, Philip Gurkaynak, Frank K. Leblebici, Yusuf Ienne, Paolo Ecole Polytech Fed Lausanne Inst Microelect & Microsyst Microelect Syst Lab CH-1015 Lausanne Switzerland

ISBN: (纸本)9781595939340

The field programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addition and multiplication operations into large multi-input addition operations, which are synthesized as compressor trees on the FPCA;the remaining portion of the circuit is synthesized on the FPGA. This paper presents a series of architectural improvements to the FPCA that reduce routing delay, increase flexibility and component utilization, and simplify the integration process. Using an FPGA containing six FPCAs, we observed average and maximum speedups of 1.60x and 2.40x on a set of arithmetic benchmarks.

关键词： FPGA field programmable Counter Array (FPCA)

来源：评论

学校读者我要写书评

暂无评论

Coarse-grained FPGA architecture for high-performance FIR filtering

Coarse-grained FPGA architecture for high-performance FIR fi...

引用

proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Anderson, James R. Sheth, Siddharth Roy, Kaushik Intel Corp Santa Clara United States

This paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar to that of a custom ASIC design, while allowing all of the basic FIR design parameters, including coefficient precision, to be configured. Previous research has already shown that FPGAs can provide a high-performance alternative to DSP processors. Experimental comparisons in this paper show that the performance and area efficiency of the proposed architecture is similar to that of custom approaches across a wide range of filter sizes and configurations.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine 24

Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar...

引用

32nd acm international symposium on field-programmable gate arrays, FPGA 2024

作者： Ray, Andy Devlin, Benjamin Quah, Fu Yong Yesantharao, Rahul Jane Street London United Kingdom Jane Street New York City United States

ISBN: (纸本)9798400704185

This paper presents a split CPU-FPGA Multi-Scalar Multiplication (MSM) engine written in Hardcaml. Hardcaml MSM was submitted to the 2022 ZPrize cryptography competition and won 1st place in the FPGA track. Hardcaml MSM targets the BLS12-377 elliptic curve and is currently the lowest-latency implementation utilizing FPGAs published. For a MSM of order 2^26 we achieve a single-round MSM latency of 5.518s and average power of 52W, with our design running at 278MHz. When performing multiple rounds of MSM with the same base points but random scalars, we are able to further mask host I/O and memory latency and reduce latency to 5.083s. This is a latency improvement of 13% over the previously fastest reported FPGA solution, and an improvement of 472% when compared to state of the art open-source CPU library gnark-crypto. © 2024 Owner/Author.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Design and implementation of a field programmable analogue array 96

Design and implementation of a field programmable analogue a...

引用

proceedings of the 1996 acm/sigda international symposium on field programmable gate arrays

作者： Bratt, Adrian Macbeth, Ian Cheshire United Kingdom

ISBN: (纸本)9780897917735

A field programmable Analogue Array (FPAA) is presented based on switched capacitor technology. The chip allows true array programming of undedicated analogue cells. There is provision for internal signal-conditional switching as part of the normal function of the array. With the presented chip it is possible to implement a very wide range of analogue signal processing functions such as data conversion, linear signal processing and non-linear functions. These functional configurations can be reconfigured and parameterised on the fly during concurrent signal processing. Very rapid prototyping of switched capacitor circuits is facilitated. The field programmable nature of the chip allows several markets/customers to be targeted simultaneously with obvious benefits in terms of both volume of sales and reduced time to market.

关键词： Linear integrated circuits

来源：评论

学校读者我要写书评

暂无评论

Eliminating the Memory Bottleneck: An FPGA-based Solution for 3D Reverse Time Migration 11

Eliminating the Memory Bottleneck: An FPGA-based Solution fo...

引用

19th Annual acm international symposium on field-programmable gate arrays

作者： Fu, Haohuan Clapp, Robert G. Tsinghua Univ Ctr Earth Syst Sci Beijing 100084 Peoples R China

ISBN: (纸本)9781450305549

Memory-related constraints (memory bandwidth, cache size) are nowadays the performance bottleneck of most computational applications. Especially in the scenario of multiple cores, the performance does not scale with the number of cores in many cases. In our work, we present our FPGA-based solution for the 3D Reverse Time Migration (RTM) algorithm. As the most computationally demanding imaging algorithm in current oil and gas exploration, RIM involves various computational challenges, such as a high demand for storage size and bandwidth, and a poor cache behavior. Combining optimizations from both the algorithmic and architectural perspectives, our FPGA-based solution manages to remove the memory constraints and provide a high performance that can scale well with the amount of computational resources available. Compared with an optimized CPU implementation using two quad-core Intel Nehalem CPUs, our solution achieves 4x speedup on two Virtex-5 FPGAs, and 8x speedup on two Virtex-6 FPGAs. Our projection demonstrates that the performance will continue to scale with the future increase of FPGA capacities.

关键词： field programmable gate arrays (FPGA) Reverse Time Migration (RTM)

来源：评论

学校读者我要写书评

暂无评论

Improving bitstream compression by modifying FPGA architecture 13

Improving bitstream compression by modifying FPGA architectu...

引用

2013 acm/sigda international symposium on field programmable gate arrays, FPGA 2013

作者： Razavi, Seyyed Ahmad Saheb Zamani, Morteza Department of Computer Engineering and Information Technology Amirkabir University of Technology Tehran Iran

ISBN: (纸本)9781450318877

The size of configuration bitstreams of field-programmable gate arrays (FPGA) is increasing rapidly. Compression techniques are used to decrease the size of bitstreams. In this paper, an appropriate bitstream format and variable symbol lengths are proposed to utilize the routing patterns for enhancing the compression efficiency. An order of inputs of multiplexers in switch modules is also proposed to improve the symbol statistics and hence, the compression efficiency. A framework to generate the bitstream and hardware description of FPGAs is developed as well. Experimental results over 20 MCNC benchmarks show that by applying the proposed approaches, the compression rate is improved by 46% on average compared to the methods with fixed symbol lengths without any area and performance degradation. © 2013 acm.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in FPGAs 12

Reducing the Cost of Floating-Point Mantissa Alignment and N...

引用

20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Moctar, Yehdhih Ould Mohammed George, Nithin Parandeh-Afshar, Hadi Ienne, Paolo Lemieux, Guy G. F. Brisk, Philip Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781450311557

In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemented using several rows of small multiplexers;unfortunately, multiplexer-based logic structures map poorly onto LUTs. FPGAs, meanwhile, contain a large number of multiplexers in the programmable routing network;these multiplexer are placed under static control of the FPGA's configuration bitstream. In this work, we modify some of the routing multiplexers in the intra-cluster routing network of a CLB in an FPGA to implement shifters for floating-point mantissa alignment and normalization;the number of CLBs required for these operations is reduced by 67%. If shifting is not required, the routing multiplexers that have been modified can be configured to operate as normal routing multiplexers, so no functionality is sacrificed. The area overhead incurred by these modifications is small, and there is no need to modify every routing multiplexer in the FPGA. Experiments show that there is no negative impact in terms of clock frequency or routability for benchmarks that do not use the dynamic multiplexers.

关键词： field programmable gate Array (FPGA) Floating-point Mantissa Alignment Normalization

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共80页 << < 4 5 6 7 8 9 10 11 12 13 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：