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23rd Asia and South Pacific design automation conference (ASP-DAC)

作者： Tille, Daniel Gottinger, Benedikt Pfannkuchen, Ulrike Graeb, Helmut Schlichtmann, Ulf Infineon Technol AG Munich Germany Tech Univ Munich Munich Germany

ISBN: (纸本)9781509006021

The 1-Pin test concept has proven to be beneficial for test cost reduction. By compacting test responses into a signature and reading them out at test end, test parallelism can be increased significantly. This reduces the test time and thus test cost. Especially cost-sensitive devices, e.g. IoT end nodes, profit. A drawback of this method is the limited capability of diagnosis due to the lack of cycle-accurate PASS/FAIL information. In this paper, we present a new approach to tackle this challenge. It enables the use of an industrial diagnosis flow for fails that occurred during 1-Pin test. For this purpose, we propose failing vector and failing cycle analysis techniques. Our approach is fault model independent and not limited to a single fault assumption. We mitigate the aliasing problem by masking. The effectiveness of our approach is shown on an investigation of real silicon fails in industrial designs.

关键词： Dictionaries Tools Circuit faults Integrated circuit modeling Silicon Pins Hardware

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A Unified Solution to Scan test Volume, Time, and Power Minimization

A Unified Solution to Scan Test Volume, Time, and Power Mini...

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23rd International conference on VLSI design/9th International conference on Embedded Systems

作者： Chen, Zhen Seth, Sharad Xiang, Dong Bhattacharya, Bhargab B. Tsinghua Univ Dept Comp Sci & Techn Beijing 100084 Peoples R China Univ Nebraska Comp Sci & Engn Lincoln NE 68588 USA Tsinghua Univ Sch Software Beijing 100084 Peoples R China Indian Stat Inst Kolkata W Bengal India

The double-tree scan-path architecture, originally proposed for low test power, is adapted to simultaneously reduce the test application time and test data volume under external testing Experimental results show signi... 详细信息

ISBN: (纸本)9781424455416

关键词： test power minimization test time reduction test data reduction Nonlinear scan

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Coverage Management with In line Assertions and Formal test Points

Coverage Management with In line Assertions and Formal Test ...

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23rd International conference on VLSI design/9th International conference on Embedded Systems

作者： Hazra, Aritra Ghosh, Priyankar Dasgupta, Pallab Chakrabarti, P. P. Indian Inst Technol Dept Comp Sci & Engn Kharagpur 721302 W Bengal India

ISBN: (纸本)9781424455416

This paper studies the problem of coverage management with two emerging formalisms in simulation based validation, namely formal specification of test points and the use of mime temporal assertions We present methods for checking whether a test-bench with mime assertion covers a set of formal test points This is particularly useful in developing verification IPs for standard on-chip protocols where the development team must make sure that the test bench provided in the verification IP checks all the important aspects of the protocol We demonstrate the efficacy of our approach over the ARM AMBA verification IP

关键词： testing

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A Channel-Sharable Built-In Self-test Scheme for Multi-Channel DRAMs 18

A Channel-Sharable Built-In Self-Test Scheme for Multi-Chann...

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23rd Asia and South Pacific design automation conference (ASP-DAC)

作者： Wu, Kuan-Te Li, Jin-Fu Lo, Chih-Yen Lai, Jenn-Shiang Kwai, Ding-Ming Chou, Yung-Fa Natl Cent Univ Dept Elect Engn Adv Reliable Syst ARES Lab Taoyuan 320 Taiwan Ind Technol Res Inst Informat & Commun Res Labs Hsinchu 310 Taiwan

ISBN: (纸本)9781509006021

Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel IG-bit DRAM by consuming about 0.003% additional area cost.

关键词： DRAM built-in self-test channel-based DRAM test March test

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Approximation-aware testing for Approximate Circuits 18

Approximation-aware Testing for Approximate Circuits

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23rd Asia and South Pacific design automation conference (ASP-DAC)

作者： Chandrasekharan, Arun Eggersgluess, Stephan Grolsse, Daniel Drechsler, Rolf Univ Bremen Grp Comp Architecture Bremen Germany DFKI GmbH Cyber Phys Syst Bremen Germany

ISBN: (纸本)9781509006021

A wide range of applications significantly benefit from the Approximate Computing (AC) paradigm in terms of speed or power reduction. AC achieves this by tolerating errors in the design. These errors are introduced into the design either manually by the designer or by approximate synthesis approaches. From here, the standard design flow is taken. Hence, the manufactured AC chip is eventually tested for production errors using well established fault models. To be precise, if the test for a test pattern fails, the AC chip is sorted out. However, from a general perspective this procedure results in throwing away chips which are perfectly fine taking into account that the considered fault (i.e. physical defect that leads to the error) can still be tolerated because of approximation. This can lead to a significant amount of yield loss. In this paper, we present an approximation-aware test methodology which can be easily integrated into the regular test flow. It is based on a pre-process to identify approximation-redundant faults. By this, we remove all potential faults that no longer need to be tested because they can be tolerated under the given error metric. Our experimental results and case studies on a wide variety of benchmark circuits show a significant potential for yield improvement.

关键词： Circuit faults Adders Measurement Production Approximate computing Integrated circuit modeling Automatic test pattern generation

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On Minimization of test Application Time for RAS

On Minimization of Test Application Time for RAS

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23rd International conference on VLSI design/9th International conference on Embedded Systems

作者： Adiga, Raghavendra Arpit, Gandhi Singh, Virendra Saluja, Kewal K. Fujiwara, Hideo Singh, Adit D. Indian Inst Sci Bangalore 560012 Karnataka India Univ Wisconsin Madison WI USA Nara Inst Sci & Technol Nara Japan Auburn Univ Auburn NY USA

ISBN: (纸本)9781424455416

Conventional Random access scan (RAS) for testing has lower test application time, low power dissipation, and low test data volume compared to standard serial scan chain based design In this paper, we present two cluster based techniques, namely, Serial Input Random Access Scan and Variable Word Length Random Access Scan to reduce test application time even further by exploiting the parallelism among the clusters and performing write operations on multiple bits Experimental results on benchmarks circuits show on an average 2-3 times speed up in test write time and average 60% reduction in write test data volume

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Impact of Temperature on test Quality

Impact of Temperature on Test Quality

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23rd International conference on VLSI design/9th International conference on Embedded Systems

作者： Jagan, Lavanya Hora, Camelia Kruseman, Bram Eichenberger, Stefan Majhi, Ananta K. Kamakoti, V. IIT Madras Dept CSE RISE Grp Madras Tamil Nadu India NXP Semicond Corp Innovat & Technol Grp Eindhoven Netherlands

ISBN: (纸本)9781424455416

The usage of more advanced, less mature processes during manufacturing of semiconductor devices has increased the need for performing unconventional types of testing, like temperature-testing, in order to maintain the same high quality levels However, performing temperature-testing is costly This paper proposes a viable low-cost alternative to temperature testing that quantifies the impact of temperature variations on the test quality and also determines optimal test conditions The test flow proposed is empirically validated on an industrial-standard die The results obtained show that majority of the defects that were originally detected by temperature-testing are also detected by the proposed test flow, thereby reducing the dependence on temperature testing to achieve zero-defect quality Details of an interesting defect behavior at cold test conditions is also presented

关键词： Defects

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Recap of the 23rd Asia and South Pacific design automation conference (ASP-DAC)

IEEE DESIGN & TEST

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IEEE design & test 2018年第3期35卷 100-101页

作者： Shin, Youngsoo Korea Adv Inst Sci & Technol Daejeon South Korea

The 23rd Asia and South Pacific design automation conference (ASP-DAC) was held at the International Convention Center, Jeju Island, South Korea, on 22–25 January 2018. ASP-DAC was founded in 1995 and has continuously offered opportunity for the researchers around Asia and South Pacific regions to communicate with each other and to get exposed to the advanced and recent technologies. This year’s event was sponsored by ACM Special Interest Group on design automation (SIGDA), the IEEE Circuits and Systems Society, and the IEEE Council on Electronic design automation. We also had two Japanese organizations, Institute of Electronics, Information and Communication Engineers and Information Processing Society of Japan, which supported the conference. We were very fortunate to have a number of corporate sponsors including Cadence, SK Hynix, Mentor, Synopsys, Entasys, Baum, and Silvaco. The conference was attended by 373 people, which is similar to when the conference was held in Chiba, Japan, last year; the largest number of attendees was from South Korea, followed by the United States, Taiwan, China, Japan, Hong Kong, and Germany.

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Optimizing Dynamic Mapping Techniques for On-Line NoC test 18

Optimizing Dynamic Mapping Techniques for On-Line NoC Test

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23rd Asia and South Pacific design automation conference (ASP-DAC)

作者： Jiang, Shuyan Wu, Qiong Chen, Shuyu Wang, Junshi Ebrahimi, Masoumeh Huang, Letian Li, Qiang Univ Elect Sci & Technol China Chengdu Sichuan Peoples R China Royal Inst Technol KTH Stockholm Sweden

ISBN: (纸本)9781509006021

With the aggressive scaling of submicron technology, intermittent faults are becoming one of the limiting factors in achieving a high reliability in Network-on-Chip (NoC). Increasing test frequency is necessary to detect intermittent faults, which in turn interrupts the execution of applications. On the other hand, the main goal of traditional mapping algorithms is to allocate applications to the NoC platform, ignoring about the test requirement. In this paper, we propose a novel testing-aware mapping algorithm (TAMA) for NoC, targeting intermittent faults on the paths between crossbars. In this approach, the idle links are identified and the components between two crossbars are tested when the application is mapped to the platform. The components can be tested if there is enough time from when the application leaves the platform and a new application enters it. The mapping algorithm is tuned to give a higher priority to the tested paths in the next application mapping. This leaves enough time to test the links and the belonging components that have not been tested in the expected time. Experiment results show that the proposed testing-aware mapping algorithm leads to a significant improvement over FF, NN, CoNA, and WeNA.

关键词： Network-on-Chip mapping algorithm intermittent fault on-line testing

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Model-based Avionic Systems testing for the Airbus Family 23

Model-based Avionic Systems Testing for the Airbus Family

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23rd IEEE european test Symposium (ETS)

作者： Peleska, Jan Univ Bremen Dept Math & Comp Sci Bremen Germany

ISBN: (纸本)9781538637289

This paper is about practical verification of Airbus avionic systems during type certification, with special focus on automated testing. The material is based on test and verification services performed for Airbus by a spinoff company of the University of Bremen, as well as on consultancy services delivered by our research group to Airbus and its suppliers. In the context of model-based systems engineering, the test automation approach is currently shifting from manual test procedure programming to model-based testing (MBT), where test cases are automatically identified in models describing the application behavior, allowing for automated test data calculation and test procedure generation. We describe the situations where today's MBT technology is already adequate to increase the effectiveness of automated testing in industry. In addition, we describe some open challenges arising from practical avionic systems testing, where satisfactory solutions still require some research effort.

关键词： model-based testing test automation model-based systems engineering avionic systems

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