Transition faults require scan tests with two functional clock cycles between a scan-in and a scan-out operation to activate the faults and propagate their effects to observable outputs. Multicycle tests, with two or ...
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ISBN:
(纸本)9781538637289
Transition faults require scan tests with two functional clock cycles between a scan-in and a scan-out operation to activate the faults and propagate their effects to observable outputs. Multicycle tests, with two or more functional clock cycles between scan operations, provide the following advantages. (1) They potentially increase the defect coverage by exercising the circuit at-speed for several functional clock cycles. (2) They allow test compaction to be achieved. (3) Multicycle tests can address features such as multiple clock domains and partial scan. (4) They create closer-to-functional operation conditions that are important for avoiding overtesting of delay faults.
The Revised Payment Services Directive (PSD2) forces retail banks to make customer accounts accessible to TPPs via standardized and secure "Access to Account" (XS2A) interfaces. Furthermore, banks have to en...
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ISBN:
(纸本)9789897585098
The Revised Payment Services Directive (PSD2) forces retail banks to make customer accounts accessible to TPPs via standardized and secure "Access to Account" (XS2A) interfaces. Furthermore, banks have to ensure that these interfaces continuously meet functional and performance requirements, hence testing is very important. A known challenge in software testing is the design of test cases. While standardized specifications and derived test cases exist, the actual implementations of XS2A interfaces often deviate, leading to the need to adapt existing or create new test cases. We apply a design science approach, including five expert interviews, to iteratively generate a concept of a test tool that enables testing of several XS2A interface implementations with the same set of test cases. The concept makes use of files mapping deviations between the standardized specification and the implemented interfaces. We demonstrate the concept's feasibility by implementing a prototype and testing its functionality in a sandbox setting.
The recent widespread popularity of computational thinking (CT) has raised the need for a reliable method for assessing it. Recent CT tests focus on programming skills rather than the analytical ability and problem-so...
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ISBN:
(纸本)9781450357074
The recent widespread popularity of computational thinking (CT) has raised the need for a reliable method for assessing it. Recent CT tests focus on programming skills rather than the analytical ability and problem-solving processes in science, philosophy and other areas of knowledge. This poster presents the results (testdesign) of an ongoing project that has developed a Psychometric Computational Thinking test (PCTT) which has three phases: testdesign, test implementation and applying the test. In regards to the PCTT design, the reliability and validity of the test were based on content and construct validity which also includes its rating scales for its application. This work makes two contributions: (1) a standardized CT testdesign incorporating psychometric techniques as well as computational techniques and (2) the inclusion of open-ended questions and their assessment with V of Aiken in order to validate responses.
As the advance of software component technology, engineers encountered different issues and challenges in testing and automation of configurable components and component-based programs. One of them is how to validate ...
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ISBN:
(纸本)1891706292
As the advance of software component technology, engineers encountered different issues and challenges in testing and automation of configurable components and component-based programs. One of them is how to validate configurable components and programs to achieve adequate test criteria and support testautomation. This paper uses a test model, known as a semantic tree, to assist engineers to model and analyze diverse composite components and configurable software in terms of configurable environments, organization structures and functions. Based on this model, well-defined test criteria are presented to address the adequate testing issues. In addition, the paper discusses two test complexity evaluation methods for configurable components and software. Furthermore, some case study results are reported to demonstrate the testing complexity of diverse configurations.
A high-level language for the description of functional tests is described. This language integrates simulation and test by providing a common source language and programming environment. Through the use of individual...
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The aim of the structural automatic test pattern generation (ATPG) is to efficiently construct a compact set of test patterns that are able do discover faults from a given structural fault model. This paper focuses on...
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ISBN:
(纸本)0818681306
The aim of the structural automatic test pattern generation (ATPG) is to efficiently construct a compact set of test patterns that are able do discover faults from a given structural fault model. This paper focuses on the usage for ATPG of a new data representation, called term trees. We designed and implemented a new term tree based ATPG algorithm with the following features: 1) 100% coverage of all nonredundant faults of the fault model, 2) a (near) minimal test set, 3) detection of circuit redundancy that disables testing for some faults, 4) a practical ATPG time and memory usage. In the paper we introduce the term trees and their structural fault model, show how to use them for effective and efficient test pattern generation and discuss some ATPG results. We also propose an effective, efficient and flexible term tree minimization algorithm and discuss some benchmark results. The term trees can be applied for many other purposes in logic design and other areas.
The space station electrical power system will be controlled by a network of distributed processors. Control software will be verified, validated, and tested in hardware and software test beds. Software test bed verif...
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The space station electrical power system will be controlled by a network of distributed processors. Control software will be verified, validated, and tested in hardware and software test beds. Software test bed verification and validation will reduce the risk of costly hardware failures. Current plans for the software test bed involve using real-time and non-real-time simulations of the power system. These simulations will address specific aspects of testing. The author discusses the current space station power system design, next-generation test bed configuration, simulations in support of the test bed, and the configuration of the simulation facility (EPS automation Lab).
Semiconductor device manufacturing depends on Structural tests to work across voltage and temperature to achieve product qualification. This paper details Vmin issues encountered on system-on-chip (SoC) for Scan and A...
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ISBN:
(纸本)9798350384406
Semiconductor device manufacturing depends on Structural tests to work across voltage and temperature to achieve product qualification. This paper details Vmin issues encountered on system-on-chip (SoC) for Scan and Array testing, how these Vmin issues were root-caused, analyzed, and resolved. This methodology is currently proven to achieve Vmin improvement in the range of 10% to 20% for structural tests and deployed on various SoC. and can be used to help other designs identify and implement these !earnings to achieve product qualification within predictable schedule.
As modern technology nodes get more and more susceptible to soft-errors, various hardened latch cells have been proposed. The added redundancy used to tolerate transient faults in the field at the same time reduces th...
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ISBN:
(纸本)9781538637289
As modern technology nodes get more and more susceptible to soft-errors, various hardened latch cells have been proposed. The added redundancy used to tolerate transient faults in the field at the same time reduces the test coverage of cell-internal production defects. Moreover, the test escapes reduce the soft-error tolerance of the defective latches. This work introduces a new soft-error vulnerability metric called Post test Vulnerability Factor that correctly measures the added vulnerability to transient faults such as particle strikes caused by undiscovered production defects within hardened latches.
Although built-in self-repair (BISR) techniques have been widely used to improve memory yield, their applications to the testing of 3D systems-on-chip (SoC) remained primarily unexplored. In this manuscript, we presen...
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ISBN:
(纸本)9798350384406
Although built-in self-repair (BISR) techniques have been widely used to improve memory yield, their applications to the testing of 3D systems-on-chip (SoC) remained primarily unexplored. In this manuscript, we present a multi-stage approach to implement BISR in 3D SoCs with an aim to (i) reduce test time by proposing a test scheduling technique satisfying given power constraints, (ii) reduce the number of BISR modules, and (iii) to place BISR circuitry in suitable layers for facilitating thermal dissipation. Experimental results on several SoC benchmarks show that our approach reduces both test time as well as the cost of BISR architecture in most cases.
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