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proceedings of the 23rd annual workshop and symposium. MICRO 23. microprogramming and microarchitecture (Cat. No.90TH0341-8)

Proceedings of the 23rd Annual Workshop and Symposium. MICRO...

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annual workshop on microprogramming and microarchitecture

Presents the front cover of the proceedings record.

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proceedings of the annual International symposium on microarchitecture, MICRO

Proceedings of the Annual International Symposium on Microar...

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23rd annual workshop and symposium on microprogramming and microarchitecture, MICRO 1990

ISBN: (纸本)0897914139

The proceedings contain 33 papers. The topics discussed include: topologies for the parallel backtracking Prolog engine;on the testing of microprogrammed processor;SMDSS - a structured microcode development and simulation;prism architecture parallel and pipeline features;a weighted technique for programmable logic devices minimization;microprogramming heritage of RISC design;a barrel shift microsystem for parallel processing;a high-level microprogrammed processor;a model of a microprogrammed functional-oriented computing unit;software pipelining: a comparison and improvement;a framework for high-speed controller design;using a lookahead window in a compaction-based parallelizing compiler;realistic scheduling: compaction for pipelined architectures;a fine-grained MIMD architecture based upon register channels;hardware implementation of a general multi-way jump mechanism;instruction sets and their implementations;a software pipelining based VLIW architecture and optimizing compiler;high-level microprogramming: an optimizing c compiler for a processing element of a cad accelerator;and SYMCAD : synthesis of microprogrammed control for automated VLSI design.

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microprogramming heritage of RISC design 23

Microprogramming heritage of RISC design

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23rd annual workshop and symposium on microprogramming and microarchitecture, MICRO 1990

作者： Shih, Liwen Computer System Design and Engineering University of Houston-Clear Lake HoustonTX77058 United States

ISBN: (纸本)0897914139

Technology impact brings Reduced Instruction Set Computer (RISC) design approach back to the stage of computer architecture evolution. While RISC architecture grab attention by their flying instruction rates, this paper summarizes the current design of micro-architectures and analyzes the tradeoffs between RISC approach and microprogramming approach especially on the vertical migration among hardware, firmware, compilation and software. RISCs' simplicity is contrasted by the regularity of microprogrammed control. The RISC design incentives are categorized into three perspectives, namely, technology-driven, application-driven, and performance-driven. Traditional firmware migration approaches are reviewed and related to RISC design philosophy as well as Writable Instruction Set Computer (WISC) concept. Research such as Firmware Migration candidates selection can be applied to RISC instruction set design. Similarly, micro-code generation and compaction research can be used to construct the smart, optimizing RISC compiler. Horizontal microcode approach is interpreted as the Very Long Instruction Word (VLIW) architecture. Incorporating in the discussion about new design trends affected by GaAs, memory technology, and super-computing a clue for the direction of future-proof micro-architecture and microprogramming is projected. © 1990 IEEE Computer Society. All rights reserved.

关键词： microprogramming

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High-level microprogramming: An optimizing C compiler for a processing element of a CAD accelerator 23

High-level microprogramming: An optimizing C compiler for a ...

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23rd annual workshop and symposium on microprogramming and microarchitecture, MICRO 1990

作者： Kenyon, Paul Agrawal, Prathima Seth, Sharad University Nebraska Lincoln United States ATandT Bell Laboratories Murray HillNJ United States

ISBN: (纸本)0897914139

The development of a high-level language compiler for a micro-programmable processing element (PE) in the MARS multicomputer is described. MARS, an MIMD message passing machine, was designed to speed up VLSI CAD and similar other non-numerical applications. The need for support of a high-level language at the PE level of a multicomputer is considered, and the choice of C as an appropriate programming language is justified. Special features found in VLSI processors are examined along with compiler support for *** retargetable compiler techniques are shown to be inadequate for the highly concurrent micro-programmable PE. These techniques must be extended for microcode generation. The design of the MARS compiler is outlined. Performance data is provided to evaluate the benefit of various compiler optimizations, and to compare compiler generated microcode to hand generated microcode in terms of space and time performance. © 1990 IEEE Computer Society. All rights reserved.

关键词： C (programming language)

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SMDSS-a structured microcode development and simulation system

SMDSS-a structured microcode development and simulation syst...

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annual workshop on microprogramming and microarchitecture

作者： D. Smati J. Hwang C. Papachristou Synopsys Inc. Mountain View CA USA Digital Equipment Corporation Hudson MA USA CS Department Case Western Reserve University Cleveland OH USA

The paper presents a software environment SMDSS for specification, simulation, and design of digital systems based on the concept of modularity in microprogramming. It provides a hardware description language SMDSL, a modular microcode generator, and a functional simulator. Besides the distinction of structural and behavioral parts in a digital system description, the language covers high level structured constructs to facilitate the control sequencing. The microcode generator implementation is based on a previously developed microprogram control architecture which has been improved to enable the presence of structured constructs. The functional simulator is developed to allow testing the design validity.< >

关键词： microprogramming Hardware Decoding Digital systems Testing Computer architecture Signal generators Control systems Buildings Writing

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microprogramming heritage of RISC design

Microprogramming heritage of RISC design

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annual workshop on microprogramming and microarchitecture

作者： L. Shih Computer System Design & Engineering University of Houston Clear Lake Houston TX USA

The paper summarizes the current design trends of micro-architectures and analyzes the tradeoffs between the RISC approach and the microprogramming approach especially on vertical migration among hardware, firmware, compilation, and software. RISCs simplicity is contrasted by the regularity of microprogrammed control. The RISC design incentives are categorized into three perspectives, namely, technology-driven, application-driven, and performance-driven. Traditional firmware migration approaches are reviewed and related to the RISC design philosophy as well as, the writable instruction set computer (WISC) concept. Research such as firmware migration candidates selection can be applied to RISC instruction set design. Similarly, micro-code generation and compaction research can be used to construct smart, optimizing RISC compilers. Horizontal microcoding is interpreted by the very long instruction word (VLIW) architecture.< >

关键词： microprogramming Reduced instruction set computing Computer aided instruction Computer architecture Clocks Hardware Optimizing compilers Pipelines Data engineering Design engineering

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High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator

High-level microprogramming: an optimizing C compiler for a ...

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annual workshop on microprogramming and microarchitecture

作者： P. Kenyon P. Agrawal S. Seth University of Nebraska-Lincoln Lincolnshire NE USA AT and T Bell Laboratories Inc. Murray Hill NJ USA

The development of a high-level language compiler for a micro-programmable processing element (PE) in the MARS multicomputer is described. MARS, an MIMD message passing machine, was designed to speed up VLSI CAD and similar other non-numerical applications. The need for support of a high-level language at the PE level of a multicomputer is considered, and the choice of C as an appropriate programming language is justified. Special features found in VLSI processors are examined along with compiler support for them. Conventional retargetable compiler techniques are shown to be inadequate for the highly concurrent micro-programmable PE. These techniques must be extended for microcode generation. The design of the MARS compiler is outlined. Performance data is provided to evaluate the benefit of various compiler optimizations, and to compare compiler generated microcode to hand generated microcode in terms of space and time performance.< >

关键词： microprogramming Optimizing compilers Acceleration Mars Very large scale integration High level languages Circuit simulation Programming profession Message passing Design automation

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A weighted technique for programmable logic devices minimization

A weighted technique for programmable logic devices minimiza...

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annual workshop on microprogramming and microarchitecture

作者： C.H. Chang H.K. Azzam Department of Electrical Engineering Tufts University Medford MA USA

A technique for minimizing the width of programmable logic devices (PLDs) is introduced. The algorithm starts with the result of the technique introduced by Das, Banerji and Chatopadhyay (1973). The solution obtained is refined to form the temporary solution, or what is called a preliminary solution. The problem of the preliminary solution is that it does not guarantee a minimum solution, because it does not use redundant classes, that are sometimes essential to the final minimum solution. The weighting technique is introduced, which gives a weight to each micro-order. The micro-orders with the largest weights are stripped from each class to form a stripped set. The stripped micro-orders are tested for compatibility, and a new set of compatibility classes are formed based on the stripped micro-orders, and the reserved classes only. Some factors are taken into consideration before the stripped micro-orders become the final collection. The procedure loops again with the new set of compatibility classes as long as reduction is obtained.< >

关键词： Programmable logic devices Read only memory Registers Minimization methods microprogramming Hardware Digital control Control systems Microprocessors Timing

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A survey on bit dimension optimization strategies of microprograms

A survey on bit dimension optimization strategies of micropr...

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annual workshop on microprogramming and microarchitecture

作者： S.R. Das A.R. Nayak Department of Electrical Engineering University of Ottawa Ottawa ONT Canada Department of Electrical Engineering Computer Engineering Carleton University Ottawa ONT Canada

Microprogram optimization is one way to increase efficiency, and optimization can be crucial in some applications. Optimization refers to a reduction of execution time of microprograms, or of the control store size, B*W, where W represents the word dimension of the control store which is the number of words of control store required for certain application, and B represents the bit dimension which is the number of bits per word of control store. The various optimization strategies can be broadly classified under four categories: bit dimension reduction, word dimension reduction, state reduction, and heuristic reduction. A survey of the various bit dimension optimization techniques has been presented by Agerwala in his 1976 paper, where the techniques are critically analyzed and compared, and the results of analysis are discussed. The paper further augments the work of Agerwala, taking into account the optimization methods developed later and hence not discussed by him. Also, the present study considers the optimization problem in the case of polyphase microinstructions in addition to that for monophase microinstructions. The prospective, current status, and future trends in this direction are also briefly outlined.< >

关键词： Hardware Size control microprogramming Computer aided instruction Encoding Systems engineering and theory Application software Optimization methods Decoding Logic design

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microprogramming heritage of RISC design 23

Microprogramming heritage of RISC design

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proceedings of the 23rd annual workshop and symposium on microprogramming and microarchitecture

作者： Liwen Shih Computer System Design & Engineering University of Houston - Clear Lake Houston Texas

ISBN: (纸本)9780897914130

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