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检索条件"任意字段=Proceedings of the 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming"

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Accurate data redistribution cost estimation in software distributed shared memory systems 01

Accurate data redistribution cost estimation in software dis...

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8th acm sigplan symposium on principles and practice of parallel programming

作者： Morris III, D.G. Lowenthal, D.K. Hewlett-Packard Company 19447 Pruneridge Avenue Cupertino CA 95014 United States

ISBN: (纸本)9781581133462

Distributing data is one of the key problems in implementing efficient distributed-memory parallel programs. the problem becomes more difficult in programs where data redistribution between computational phases is considered. the global data distribution problem is to find the optimal distribution in multi-phase parallel programs. Solving this problem requires accurate knowledge of data redistribution cost. We are investigating this problem in the context of a software distributed shared memory (SDSM) system, in which obtaining accurate redistribution cost estimates is difficult. this is because SDSM communication is implicit: It depends on access patterns, page locations, and the SDSM consistency protocol. We have developed integrated compile- and run-time analysis for SDSM systems to determine accurate redistribution cost estimates with low overhead. Our resulting system, SUIF-Adapt, can efficiently and accurately estimate execution time, including redistribution, to within 5% of the actual time in all of our test cases and is often much closer. these precise costs enable SUIF-Adapt to find efficient global data distributions in multiple-phase programs.

关键词： parallel processing systems

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DAPPLE: A pipelined data parallel approach for training large models 21

DAPPLE: A pipelined data parallel approach for training larg...

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26th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2021

作者： Fan, Shiqing Rong, Yi Meng, Chen Cao, Zongyan Wang, Siyu Zheng, Zhen Wu, Chuan Long, Guoping Yang, Jun Xia, Lixue Diao, Lansong Liu, Xiaoyong Lin, Wei Alibaba Group China

ISBN: (纸本)9781450382946

It is a challenging task to train large DNN models on sophisticated GPU platforms with diversified interconnect capabilities. Recently, pipelined training has been proposed as an effective approach for improving device utilization. However, there are still several tricky issues to address: improving computing efficiency while ensuring convergence, and reducing memory usage without incurring additional computing costs. We propose DAPPLE, a synchronous training framework which combines data parallelism and pipeline parallelism for large DNN models. It features a novel parallelization strategy planner to solve the partition and placement problems, and explores the optimal hybrid strategies of data and pipeline parallelism. We also propose a new runtime scheduling algorithm to reduce device memory usage, which is orthogonal to re-computation approach and does not come at the expense of training throughput. Experiments show that DAPPLE planner consistently outperforms strategies generated by PipeDream's planner by up to 3.23× speedup under synchronous training scenarios, and DAPPLE runtime outperforms GPipe by 1.6× speedup of training throughput and saves 12% of memory consumption at the same time. © 2021 acm.

关键词： Scheduling algorithms

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An ownership policy and deadlock detector for promises 21

An ownership policy and deadlock detector for promises

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26th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2021

作者： Voss, Caleb Sarkar, Vivek Georgia Institute of Technology United States

ISBN: (纸本)9781450382946

Task-parallel programs often enjoy deadlock freedom under certain restrictions, such as the use of structured join operations, as in Cilk and X10, or the use of asynchronous task futures together with deadlock-avoiding policies such as Known Joins or Transitive Joins. However, the promise, a popular synchronization primitive for parallel tasks, does not enjoy deadlock-freedom guarantees. Promises can exhibit deadlock-like bugs;however, the concept of a deadlock is not currently well-defined for promises. To address these challenges, we propose an ownership semantics in which each promise is associated to the task which currently intends to fulfill it. Ownership immediately enables the identification of bugs in which a task fails to fulfill a promise for which it is responsible. Ownership further enables the discussion of deadlock cycles among tasks and promises and allows us to introduce a robust definition of deadlock-like bugs for promises. Cycle detection in this context is non-trivial because it is concurrent with changes in promise ownership. We provide a lock-free algorithm for precise runtime deadlock detection. We show how to obtain the memory consistency criteria required for the correctness of our algorithm under TSO and the Java and C++ memory models. An evaluation compares the execution time and memory usage overheads of our detection algorithm on benchmark programs relative to an unverified baseline. Our detector exhibits a 12% (1.12×) geometric mean time overhead and a 6% (1.06×) geometric mean memory overhead, which are smaller overheads than in past approaches to deadlock cycle detection. © 2021 acm.

关键词： parallel programming

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Data structures for task-based priority scheduling 14

Data structures for task-based priority scheduling

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2014 19th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2014

作者： Wimmer, Martin Versaci, Francesco Träff, Jesper Larsson Cederman, Daniel Tsigas, Philippas Faculty of Informatics Parallel Computing Vienna University of Technology 1040 Vienna/Wien Austria Computer Science and Engineering Chalmers University of Technology 412 96 Göteborg Sweden

ISBN: (纸本)9781450326568

We present three lock-free data structures for priority task scheduling: a priority work-stealing one, a centralized one with ρ-relaxed semantics, and a hybrid one combining both concepts. With the single-source shortest path (SSSP) problem as example, we show how the different approaches affect the prioritization and provide upper bounds on the number of examined nodes. We argue that priority task scheduling allows for an intuitive and easy way to parallelize the SSSP problem, notoriously a hard task. Experimental evidence supports the good scalability of the resulting algorithm. the larger aim of this work is to understand the trade-offs between scalability and priority guarantees in task scheduling systems. We show that ρ-relaxation is a valuable technique for improving the first, while still allowing semantic constraints to be satisfied: the lock-free, hybrid κ-priority data structure can scale as well as work-stealing, while still providing strong priority scheduling guarantees, which depend on the parameter κ. Our theoretical results open up possibilities for even more scalable data structures by adopting a weaker form of ρ-relaxation, which still enables the semantic constraints to be respected.

关键词： Scalability

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Merchandiser: Data Placement on Heterogeneous Memory for Task-parallel HPC Applications with Load-Balance Awareness 23

Merchandiser: Data Placement on Heterogeneous Memory for Tas...

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28th acm sigplan Annual symposium on principles and practice of parallel programming, PPoPP 2023

作者： Xie, Zhen Liu, Jie Li, Jiajia Li, Dong University of California Argonne National Laboratory Merced United States University of California Merced United States North Carolina State University United States

ISBN: (纸本)9798400700156

the emergence of heterogeneous memory (HM) provides a cost-effective and high-performance solution to memory-consuming HPC applications. Deciding the placement of data objects on HM is critical for high performance. We reveal a performance problem related to data placement on HM. the problem is manifested as load imbalance among tasks in task-parallel HPC applications. the root of the problem comes from being unaware of parallel-task semantics and an incorrect assumption that bringing frequently accessed pages to fast memory always leads to better performance. To address this problem, we introduce a load balance-aware page management system, named Merchandiser. Merchandiser introduces task semantics during memory profiling, rather than being application-agnostic. Using the limited task semantics, Merchandiser effectively sets up coordination among tasks on the usage of HM to finish all tasks fast instead of only considering any individual task. Merchandiser is highly automated to enable high usability. Evaluating with memory-consuming HPC applications, we show that Merchandiser reduces load imbalance and leads to an average of 17.1% and 15.4% (up to 26.0% and 23.2%) performance improvement, compared with a hardware-based solution and an industry-quality software-based solution. © 2023 acm.

关键词： Semantics

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Data locality and load balancing in COOL 93

Data locality and load balancing in COOL

引用

4th acm sigplan symposium on principles and practice of parallel programming, PPOPP 1993

作者： Chandra, Rohit Gupta, Anoop Hennessy, John L. Center for Integrated Systems Stanford University StanfordCA94305 United States

ISBN: (纸本)0897915895

Large-scale shared memory multiprocessors typically support a multilevel memory hierarchy consisting of per-processor caches, a local portion of shared memory, and remote shared memory. On such machines, the performance of parallel programs is often limited by the high latency of remote memory references. In this paper we explore how knowledge of the underlying memory hierarchy can be used to schedule computation and distribute data structures, and thereby improve data locality. Our study is done in the context of COOL, a concurrent object-oriented language developed at Stanford. We develop abstractions for the programmer to supply optional information about the data reference patterns of the program. this information is used by the runtime system to distribute tasks and objects so that the tasks execute close (in the memory hierarchy) to the objects they reference. We demonstrate the effectiveness of these techniques by applying them to several applications chosen from the SPLASH parallel benchmark suite. Our experience suggests that improving data locality can be simple through a combination of programmer abstractions and smart runtime scheduling.

关键词： Object oriented programming

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thread to Strand Binding of parallel Network Applications in Massive Multi-threaded Systems

Thread to Strand Binding of Parallel Network Applications in...

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Radojkovic, Petar Cakarevic, Vladimir Verdu, Javier Pajuelo, Alex Cazorla, Francisco J. Nemirovsky, Mario Valero, Mateo Univ Politecn Cataluna E-08028 Barcelona Spain CSIC Madrid Spain

ISBN: (纸本)9781605587080

In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a single level of resource sharing, such as pure-SMT or pure-CMP processors. Once the operating system selects the set of applications to simultaneously schedule on the processor (workload), each application/thread must be assigned to one of the hardware contexts (strands). We call this last scheduling step the thread to Strand Binding or TSB. In this paper, we show that the TSB impact on the performance of processors with several levels of shared resources is high. We measure a variation of up to 59% between different TSBs of real multithreaded network applications running on the UltraSPARC T2 processor which has three levels of resource sharing. In our view, this problem is going to be more acute in future multithreaded architectures comprising more cores, more contexts per core, and more levels of resource sharing. We propose a resource-sharing aware TSB algorithm (TSBSched) that significantly facilitates the problem of thread to strand binding for software-pipelined applications, representative of multithreaded network applications. Our systematic approach encapsulates both, the characteristics of multithreaded processors under the study and the structure of the software pipelined applications. Once calibrated for a given processor architecture, our proposal does not require hardware knowledge on the side of the programmer, nor extensive profiling of the application. We validate our algorithm on the UltraSPARC T2 processor running a set of real multithreaded network applications on which we report improvements of up to 46% compared to the current state-of-the-art dynamic schedulers.

关键词： Algorithms Measurement Performance Process Scheduling Simultaneous Multithreading CMT UltraSPARC T2

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the STAPL parallel Container Framework 11

The STAPL Parallel Container Framework

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16th acm symposium on principles and practice of parallel programming

作者： Tanase, Gabriel Buss, Antal Fidel, Adam Harshvardhan Papadopoulos, Ioannis Pearce, Olga Smith, Timmie thomas, Nathan Xu, Xiabing Mourad, Nedal Vu, Jeremy Bianco, Mauro Amato, Nancy M. Rauchwerger, Lawrence Texas A&M Univ Parasol Lab Dept Comp Sci & Engn College Stn TX 77843 USA

ISBN: (纸本)9781450301190

the Standard Template Adaptive parallel Library (STAPL) is a parallel programming infrastructure that extends C++ with support for parallelism. It includes a collection of distributed data structures called pContainers that are thread-safe, concurrent objects, i.e., shared objects that provide parallel methods that can be invoked concurrently. In this work, we present the STAPL parallel Container Framework (PCF), that is designed to facilitate the development of generic parallel containers. We introduce a set of concepts and a methodology for assembling a pContainer from existing sequential or parallel containers, without requiring the programmer to deal with concurrency or data distribution issues. the PCF provides a large number of basic parallel data structures (e.g., pArray, pList, pVector, pMatrix, pGraph, pMap, pSet). the PCF provides a class hierarchy and a composition mechanism that allows users to extend and customize the current container base for improved application expressivity and performance. We evaluate STAPL pContainer performance on a CRAY XT4 massively parallel system and show that pContainer methods, generic pAlgorithms, and different applications provide good scalability on more than 16,000 processors.

关键词： parallel programming Languages Libraries Data Structures Languages Design Performance

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Compiling CHR to parallel hardware 12

Compiling CHR to parallel hardware

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14th symposium on principles and practice of Declarative programming, PPDP 2012

作者： Triossi, Andrea Orlando, Salvatore Raffaetà, Alessandra Frühwirth, thom DAIS Università Ca'Foscari Venezia Italy Inst. for Software Engineering and Compiler Construction Ulm University Germany

ISBN: (纸本)9781450315227

this paper investigates the compilation of a committed-choice rulebased language, Constraint Handling Rules (CHR), to specialized hardware circuits. the developed hardware is able to turn the intrinsic concurrency of the language into parallelism. Rules are applied by a custom executor that handles constraints according to the best degree of parallelism the implemented CHR specification can offer. Our framework deploys the target digital circuits through the Field Programmable Gate Array (FPGA) technology, by first compiling the CHR code fragment into a low level hardware description language. We also discuss the realization of a hybrid CHR interpreter, consisting of a software component running on a general purpose processor, coupled with a hardware accelerator. the latter unburdens the processor by executing in parallel the most computational intensive CHR rules directly compiled in hardware. Finally the performance of a prototype system is evaluated by time efficiency measures. Copyright © 2012 acm.

关键词： Field programmable gate arrays (FPGA)

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LogP: Towards a realistic model of parallel computation 93

LogP: Towards a realistic model of parallel computation

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4th acm sigplan symposium on principles and practice of parallel programming, PPOPP 1993

作者： Culler, David Karp, Richard Patterson, David Sahay, Abhijit Erik Schauser, Klaus Santos, Eunice Subramonian, Ramesh Von Eicken, thorsten Computer Science Division University of California Berkeley United States International Computer Science Institute Berkeley United States

ISBN: (纸本)0897915895

A vast body of theoretical research has focused either on overly simplistic models of parallel computation, notably the PRAM, or overly specific models that have few representatives in the real world. Both kinds of models encourage exploitation of formal loopholes, rather than rewarding development of techniques that yield performance across a range of current and future parallel machines. this paper offers a new parallel machine model, called LogP, that reflects the critical technology trends underlying parallel computers. It is intended to serve as a basis for developing fast, portable parallel algorithms and to offer guidelines to machine designers. Such a model must strike a balance between detail and simplicity in order to reveal important bottlenecks without making analysis of interesting problems intractable. the model is based on four parameters that specify abstractly the computing bandwidth, the communication bandwidth, the communication delay, and the efficiency of coupling communication and computation. Portable parallel algorithms typically adapt to the machine configuration, in terms of these parameters. the utility of the model is demonstrated through examples that are implemented on the CM-5. © 1993 acm.

关键词： parallel algorithms

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